Semiconductor device and method of manufacturing the same

• US 10,014,393 B2
• Filed: 11/25/2016
• Issued: 07/03/2018
• Est. Priority Date: 06/08/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Seung Min, Suh, Dong Chan, Yang, Jung Gil, Bae, Geum Jong, Song, Woo Bin
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US15/361,110
• Publication Number:
  US 20170358665A1
• Time in Patent Office: 585 Days
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of manufacturing semiconductor device includes forming a plurality of sacrificial layers and a plurality of semiconductor layers repeatedly and alternately stacked on a substrate, partially removing the sacrificial layers, forming spacers in removed regions of the sacrificial layers, and replacing remaining portions of the sacrificial layers with a gate electrode. Each of the sacrificial layers includes first portions disposed adjacent to the plurality of semiconductor layers and a second portions disposed between the first portions. The second portion having a different composition from the first portions.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of sacrificial layers and a plurality of semiconductor layers on a substrate, the semiconductor layers and the sacrificial layers being repeatedly and alternately stacked on the substrate;

partially removing the sacrificial layers;

forming spacers in removed regions of the sacrificial layers; and

replacing remaining portions of the sacrificial layers with a gate electrode,

wherein each of the sacrificial layers includes first portions disposed adjacent to the semiconductor layers and a second portion disposed between the first portions, the second portion having a different composition from the first portions,

wherein the sacrificial layers include silicon germanium, and a germanium content of the first portions is higher than a germanium content of the second portion, and

wherein the first portions include impurities.

2. The method according to claim 1, wherein partially removing the sacrificial layers includes laterally etching the sacrificial layers, and an etch rate of the first portions is higher than an etch rate of the second portion.

3. The method according to claim 1, wherein the germanium content of the first portions is 5% to 10% higher than the germanium content of the second portion.

4. The method according to claim 1, wherein the germanium content of the first portions is constant, and the germanium content of the second portion decreases toward a center of the second portion.

5. The method according to claim 1, wherein each of the sacrificial layers further comprises a boundary part, the boundary part disposed between the first portions and the second portion, and

the boundary part includes a germanium content decreasing toward the second portion.

6. The method according to claim 1, wherein the germanium content of the first portions decreases toward the second portion, and

the germanium content of the second portion is constant.

7. The method according to claim 1, wherein a thickness of each of the first portions is smaller than a thickness of the second portion.

8. A method of manufacturing a semiconductor device, the method comprising:

forming, on a substrate, a fin structure in which a plurality of sacrificial patterns and a plurality of semiconductor patterns are alternately stacked on each other, wherein each of the sacrificial patterns includes a first portion disposed adjacent to each of the plurality of semiconductor patterns and a second portion having a different composition from the first portion;

forming a dummy gate on the fin structure;

forming a first spacer on opposite sidewalls of the dummy gate;

etching the sacrificial patterns and the semiconductor patterns using the dummy gate and the first spacer as an etch mask to form a plurality of sacrificial sheets and a plurality of nanosheets;

etching sidewalls of the sacrificial sheets to form a spacer space;

forming a second spacer in the spacer space;

forming a source/drain region connected to the nanosheets;

removing the dummy gate and the sacrificial sheets;

forming a gate insulating layer; and

forming a gate electrode,

wherein each of the sacrificial patterns include silicon germanium, and a germanium content of the first portions is about 5% to about 10% higher than a germanium content of the second portion.

9. The method according to claim 8, wherein the germanium content of the first portion is constant, and the germanium content of the second portion decreases toward a center of the second portion.

10. The method according to claim 8, wherein each of the sacrificial patterns further comprises a boundary part, the boundary part is disposed between the first portion and the second portion, and

the boundary part includes a germanium content decreasing toward the second portion.

11. The method according to claim 8, wherein the germanium content of the first portion decreases in a direction toward the second portion, and the germanium content of the second portion is constant.

12. A method of manufacturing a semiconductor device, the method comprising:

forming a stacked structure disposed on a substrate, the stacked structure including a plurality of semiconductor layers and a plurality of sacrificial layers repeatedly and alternately stacked, wherein sidewalls of the sacrificial layers have a concave shape structure;

forming spacers in spaces provided by the concave shape structures;

removing the sacrificial layers to form openings; and

forming a gate electrode in the openings,

wherein each of the sacrificial layers includes first portions disposed adjacent to the semiconductor layers and a second portion disposed between the first portions, the second portion having a different composition from at least one of the first portions, and

wherein a depth of the concave shape structure is less than about 2 nm.

13. The method according to claim 12, wherein the sacrificial layers include silicon germanium, and a germanium content of the first portions is higher than a germanium content of the second portion.

14. The method according to claim 12, wherein a thickness of each of the sacrificial layers is greater than a thickness of each of the semiconductor layers.

15. The method according to claim 13, wherein the germanium content of the first portions is 5% to 10% higher than the germanium content of the second portion.