MOS-gated power devices, methods, and integrated circuits

• US 10,014,404 B2
• Filed: 01/22/2015
• Issued: 07/03/2018
• Est. Priority Date: 12/01/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US14/603,181
• Publication Number:
  US 20150214350A1
• Time in Patent Office: 1,258 Days
• Field of Search: 257329, 257330, 257331, 257332, 257E29257, 438270, 438271, 438589
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.

Claims

1. A substantially vertical device comprising:

an insulated trench having a sidewall;

a gate electrode;

a lightly doped diffusion layer adjacent to said sidewall of said insulated trench such that a voltage bias applied to the gate electrode can induce inversion in said lightly doped diffusion layer to thereby create a channel;

intentionally introduced permanent electrostatic charge positioned near said sidewall; and

a conductive shield layer which is positioned above said insulated trench, and not electrically connected to said gate.

2. The vertical device of claim 1, wherein said gate electrode comprise a plurality of gate electrodes and wherein said gate electrodes are positioned horizontally displaced from said insulated trench.

3. The device of claim 1, built in a semiconductor structure which includes an epitaxial layer over an N+ buried layer over a P+ substrate, wherein said buried layer is contacted by a sinker diffusion.

4. A substantially vertical device comprising:

a first-conductivity-type source region;

a second-conductivity-type body region separating said source region from a drain region;

a gate electrode positioned such that when a voltage bias is applied to said gate electrode, an inversion region is induced in said body region;

a vertical insulation trench through said body region; and

a first-conductivity-type lightly-doped diffusion in said body region along the sidewalls of said vertical insulation trench.

5. The vertical device of claim 4, further comprising permanent electrostatic charge positioned along an exterior edge within said vertical insulation trench.

6. The vertical device of claim 4, wherein said vertical insulation trench is positioned between two gate electrodes and further comprising a shield electrode between said gate electrodes and above said vertical insulation trench.

7. The vertical device of claim 4, wherein said body region includes a punch-through diffusion between the source region and the lightly-doped diffusion.

8. The vertical device of claim 4, wherein said gate electrode includes a silicide layer.

9. The device of claim 4, built in a semiconductor structure which includes an epitaxial layer over an N+ buried layer over a P+ substrate, wherein said buried layer is contacted by a sinker diffusion.

10. A vertical device comprising:

a first-conductivity-type source region;

a second-conductivity-type body region separating said source region from a drain region;

a gate electrode positioned such that when a voltage bias is applied to said gate electrode, an inversion region is induced in said body region;

a vertical insulation trench through said body region;

intentionally introduced permanent electrostatic charge positioned along an exterior edge within said vertical insulation trench, and

a first-conductivity-type lightly-doped diffusion in said body region along the sidewalls of said vertical insulation trench.

11. The vertical device of claim 10, wherein said vertical insulation trench is positioned between two gate electrodes and further comprising a shield electrode between said gate electrodes and above said vertical insulation trench.

12. The vertical device of claim 10, wherein said body region includes a punch-through diffusion between the source region and the lightly-doped diffusion.

13. The vertical device of claim 10, wherein said gate electrode includes a silicide layer.