Micro-electro-mechanical systems (MEMS), apparatus, and operating methods thereof

• US 10,014,870 B2
• Filed: 01/06/2016
• Issued: 07/03/2018
• Est. Priority Date: 09/09/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Yung-Chow, Huang, Wen-Hung, Lin, Yu-Wei
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US14/989,056
• Publication Number:
  US 20160118993A1
• Time in Patent Office: 909 Days
• Field of Search: 341118, 341120, 341143, 341155, 341172
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/0626 by filtering
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 3/30 Delta-sigma modulation

Abstract

A method that comprises converting a first electrical signal to a second electrical signal using a converter coupled between a micro-mechanical structure and an analog-to-digital converter (ADC). The method also comprises actuating a switch to selectively interpolate at least one datum between two neighboring converted second electrical signals based on a selected clock signal, wherein the selected clock signal is one of a plurality of clock signals, each clock signals of the plurality of clock signals has a corresponding frequency, and the selected clock signal corresponds to an operating mode of the micro-mechanical structure.

Claims

1. A method comprising:

converting a first electrical signal to a second electrical signal using a converter coupled between a micro-mechanical structure and an analog-to-digital converter (ADC), and

actuating a switch to selectively interpolate at least one datum between two neighboring converted second electrical signals based on a selected clock signal,

wherein the selected clock signal is one of a plurality of clock signals, each clock signal of the plurality of clock signals has a corresponding frequency, and the selected clock signal corresponds to an operating mode of the micro-mechanical structure.

2. The method of claim 1, further comprising:

determining if the micro-mechanical structure operates at a power saving mode, a normal mode or a high performance mode.

3. The method of claim 1, further comprising:

detecting if an intermediate signal between the converter and the ADC is the substantially smaller than a predetermined value for a predetermined interval.

4. The method of claim 1, wherein the operating mode of the micro-mechanical is a power saving mode if the first electrical signal is substantially smaller than a predetermined value for a predetermined interval.

5. The method of claim 1, wherein the actuating the switch to selectively interpolate the at least one datum is performed if the operating mode of the micro-mechanical structure is a power saving mode.

6. The method of claim 1, further comprising:

dividing a higher sampling frequency of the selected clock signal into a lower sampling frequency, wherein the higher sampling frequency is not substantially smaller than a predetermined value for a predetermined interval.

7. The method of claim 1, wherein the actuating the switch to selectively interpolate at least one datum comprises:

smoothing the two neighboring converted signals.

8. A micro-electro-mechanical system (MEMS) comprising:

a micro-mechanical structure capable of generating a first electrical signal;

an analog-to-digital converter (ADC) coupled with the micro-mechanical structure to convert the first electrical signal to at least one digital signal, the ADC being configured to demodulate a high-pass signal; and

a frequency divider coupled with the micro-mechanical structure and the ADC,

wherein the MEMS is free of an amplifier between the micro-mechanical structure and the ADC.

9. The MEMS of claim 8, further comprising:

a complementary metal-oxide-semiconductor (CMOS) circuit, the CMOS circuit electrically coupled with the micro-mechanical structure;

a digital shield feature positioned between the CMOS circuit and the micro-mechanical structure; and

an analog shield feature positioned between the CMOS circuit and the micro-mechanical structure.

10. The MEMS of claim 8, further comprising:

a converter configured to convert the first electrical signal to a second electrical signal;

a modulator configured to provide a carrier signal having a frequency higher than a frequency of the first electrical signal;

a multi-rate controller coupled with the frequency divider; and

an interpolation filter coupled with the frequency divider, the interpolation filter configured to receive at least one clock signal from the frequency divider and to smooth at least two digital signals from the ADC.

11. The MEMS of claim 10, wherein the converter is a capacitance-to-voltage converter or a capacitance-to-current converter.

12. The MEMS of claim 10, further comprising:

a detector coupled with the multi-rate controller and the converter, the detector configured to detect if the second electrical signal is substantially smaller than a predetermined value for a predetermined interval.

13. The MEMS of claim 10, wherein the interpolation filter comprises at least one comb filter and at least one integrator, the at least one comb filter being configured to receive a first clock signal, the at least one integrator being configured to receive a second clock signal.

14. The MEMS of claim 10, wherein the ADC is coupled with two switches, and one of the two switches is coupled with the interpolation filter.

15. An apparatus comprising:

at least one processor coupled with a micro-electro-mechanical system (MEMS); and

at least one memory including computer program code for one or more programs,

the at least one memory and the computer program configured to, with the at least one processor, cause the MEMS to;

convert analog signals to digital signals, wherein the analog signals are generated from a micro-mechanical structure; and

selectively interpolate at least one datum between the two converted digital signals based on a clock signal selectable from a plurality of clock signals, the clock signals of the plurality of clock signals having clock signal frequencies that differ from one another.

16. The apparatus of claim 15, wherein the MEMS is controlled by the at least one processor, the MEMS being configured to operate at a power saving mode, a normal mode or a high performance mode.

17. The apparatus of claim 15, wherein the analog signals are converted to voltage signals, current signals, or combinations thereof.

18. The apparatus of claim 15, wherein the MEMS comprises:

a micro-mechanical structure;

a complementary metal-oxide-semiconductor (CMOS) circuit, the CMOS circuit including an analog-to-digital converter (ADC);

a digital shield feature positioned between the CMOS circuit and the micro-mechanical structure; and

an analog shield feature positioned between the CMOS circuit and the micro-mechanical structure.

19. The apparatus of claim 18, wherein the digital shield feature is coupled with the analog shield feature through a connection region, the connection region having a pattern substantially equal to at least a portion of a routing pattern of at least one metallic layer of the CMOS circuit.

20. The apparatus of claims 15, wherein the MEMS is free of at least one of an amplifier, a low-pass filter, or a demodulator.