SM4 acceleration processors, methods, systems, and instructions

• US 10,015,010 B2
• Filed: 12/01/2016
• Issued: 07/03/2018
• Est. Priority Date: 07/22/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gueron, Shay, Krasnov, Vlad
• Primary Examiner(s): Armouche, Hadi
• Assistant Examiner(s): STEINLE, ANDREW J
• Application Number:
  US15/366,556
• Publication Number:
  US 20170085370A1
• Time in Patent Office: 579 Days
• Field of Search: None
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30156 Special purpose encoding of instructions, e.g. Gray coding
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/24 Key scheduling, i.e. generating round keys or sub-keys for block encryption
• CPC Class Codes: H04L 2209/80 Wireless network architectures or network communication protocols for wireless network security H04W12/00
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]

Abstract

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

Claims

1. A processor comprising:

a plurality of packed data registers;

a decode unit to decode an instruction, the instruction to indicate one or more source packed data operands, the one or more source packed data operands to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values; and

an execution unit coupled with the decode unit and coupled with the plurality of the packed data registers, the execution unit, in response to the decode of the instruction, to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

2. The processor of claim 1, in which the decode unit is to decode the instruction that is to indicate a first 128-bit source packed data operand that is to have the four 32-bit results of the four prior SM4 cryptographic rounds, and that is to indicate a second 128-bit source packed data operand that is to have the four 32-bit values.

3. The processor of claim 1, in which the four 32-bit results of the four prior SM4 cryptographic rounds are to be arranged according to round order in a source packed data operand.

4. The processor of claim 1, in which the 32-bit values and the 32-bit results for corresponding rounds are to be stored in corresponding data elements of first and second source packed data operands.

5. The processor of claim 1, in which the decode unit is to decode the instruction in which the four 32-bit results of the four prior SM4 cryptographic rounds are to be four 32-bit results of four prior SM4 encryption rounds and in which the four 32-bit values are to be four 32-bit round keys for the four prior SM4 encryption rounds, and in which the execution unit is to store the four 32-bit results of the four immediately subsequent and sequential rounds which are to be four 32-bit results of four immediately subsequent and sequential SM4 encryption rounds.

6. The processor of claim 1, in which the decode unit is to decode the instruction in which the four 32-bit results of the four prior SM4 cryptographic rounds are to be four 32-bit results of four prior SM4 decryption rounds and in which the four 32-bit values are to be four 32-bit round keys for the four prior SM4 decryption rounds, and in which the execution unit is to store the four 32-bit results of the four immediately subsequent and sequential rounds which are to be four 32-bit results of four immediately subsequent and sequential SM4 decryption rounds.

7. The processor of claim 1, in which the decode unit is to decode the instruction in which the four 32-bit results of the four prior SM4 cryptographic rounds are to be four 32-bit round keys for four prior SM4 key expansion rounds and in which the four 32-bit values are to be four 32-bit key generation constants for the four prior SM4 key expansion rounds, and in which the execution unit is to store the four 32-bit results of the four immediately subsequent and sequential rounds which are to be four 32-bit round keys for four immediately subsequent and sequential SM4 key expansion rounds.

8. The processor of claim 1, in which the decode unit is to decode the instruction that is to indicate a first source packed data operand that is to include:

a first 32-bit result of a fourth prior SM4 cryptographic round in bits [31;

0];

a second 32-bit result of a third prior SM4 cryptographic round in bits [63;

32];

a third 32-bit result of a second prior SM4 cryptographic round in bits [95;

64]; and

a fourth 32-bit result of an immediately prior SM4 cryptographic round in bits [127;

96].

9. The processor of claim 8, in which the execution unit in response to the decode of the instruction is to store a result packed data that is to include:

a first 32-bit result of a fourth most recent SM4 cryptographic round in bits [31;

0] of a destination packed data register;

a second 32-bit result of a third most recent SM4 cryptographic round in bits [63;

32] of the destination packed data register;

a third 32-bit result of a second most recent SM4 cryptographic round in bits [95;

64] of the destination packed data register; and

a fourth 32-bit result of a most recent SM4 cryptographic round in bits [127;

96] of the destination packed data register.

10. The processor of claim 1, in which the decode unit is to decode the instruction that is to have one or more bits to specify whether the four immediately subsequent and sequential SM4 cryptographic rounds are cipher rounds or key expansion rounds.

11. The processor of claim 1, wherein the execution unit, in response to the decode of the instruction, for each of the four immediately subsequent and sequential SM4 cryptographic rounds, is to perform a first set of exclusive OR (XOR) operations, a non-linear substitution function operation, a linear substitution function operation including XOR and rotate operations, and an XOR operation.

12. The processor of claim 1, in which the execution unit, in response to the decode of the instruction, is to store the four 32-bit results of the four immediately subsequent and sequential SM4 cryptographic rounds in a destination packed data register of the plurality of packed data registers which is to be explicitly specified by the instruction separately than all of the one or more source packed data operands.

13. The processor of claim 1, in which the execution unit, in response to the decode of the instruction, is to store the four 32-bit results of the four immediately subsequent and sequential SM4 cryptographic rounds in a destination packed data register of the plurality of packed data registers that is implicitly to be the same as a storage location used for one of the one or more source packed data operands.

14. A method in a processor comprising:

receiving an instruction, the instruction indicating one or more source packed data operands, the one or more source packed data operands having four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values; and

storing four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location in response to the instruction, the destination storage location indicated by the instruction.

15. The method of claim 14, wherein storing comprises storing the four 32-bit results of the four immediately subsequent and sequential SM4 cryptographic rounds in a 128-bit packed data operand.

16. The method of claim 14, wherein storing comprises storing the four 32-bit results of the four immediately subsequent and sequential SM4 cryptographic rounds arranged according to round order.

17. The method of claim 14, wherein storing comprises storing the four 32-bit results of the four immediately subsequent and sequential SM4 cryptographic rounds which are four immediately subsequent and sequential SM4 encryption rounds.

18. The method of claim 14, wherein storing comprises storing, as the four 32-bit results of the four immediately subsequent and sequential SM4 cryptographic rounds, four 32-bit round keys for the four immediately subsequent and sequential SM4 cryptographic rounds which are key expansion rounds.

19. The method of claim 14, wherein receiving comprises receiving the instruction having one or more bits to specify whether the four immediately subsequent and sequential SM4 cryptographic rounds are cipher rounds or key expansion rounds.

20. The method of claim 14, further comprising generating each of the four 32-bit results of the four immediately subsequent and sequential SM4 cryptographic rounds including performing, for each round, a first set of exclusive OR (XOR) operations, a non-linear substitution operation, a linear substitution operation, and an XOR operation.

21. A processor comprising:

a plurality of packed data registers, wherein each of the packed data registers is to store at least 128-bits;

a decode unit to decode an instruction, the instruction to indicate a first 128-bit source packed data, a second 128-bit source packed data, and a destination packed data register of the plurality of packed data registers, the first 128-bit source packed data to include four 32-bit results of four prior SM4 encryption rounds, the second 128-bit source packed data to include four 32-bit round keys for the four prior SM4 encryption rounds; and

an execution unit coupled with the decode unit, and coupled with the plurality of the packed data registers, the execution unit, in response to the decode of the instruction, to store a 128-bit result packed data in the destination packed data register, the 128-bit result packed data to include four 32-bit results of four immediately subsequent and sequential SM4 encryption rounds.

22. The processor of claim 21, in which the four 32-bit results of four prior SM4 encryption rounds are to be arranged according to round order.

23. The processor of claim 22, in which the four 32-bit round keys for the four prior SM4 encryption rounds are to be arranged according to round order.

24. The processor of claim 21, in which the four 32-bit round keys and the four 32-bit results of four prior SM4 encryption rounds for corresponding rounds are to be stored in corresponding data element positions of the first and second 128-bit source packed data.

25. The processor of claim 21, in which the decode unit is to decode the instruction that is to have one or more bits to flexibly specify that the four immediately subsequent and sequential SM4 encryption rounds are cipher rounds instead of key expansion rounds.

26. A processor comprising:

a plurality of packed data registers, wherein each of the packed data registers is to store at least 128-bits;

a decode unit to decode an instruction, the instruction to indicate a first 128-bit source packed data, a second 128-bit source packed data, and a destination packed data register of the plurality of packed data registers, the first 128-bit source packed data to include four 32-bit round keys for four prior SM4 key expansion rounds, the second 128-bit source packed data to include four 32-bit key generation constants for the four prior SM4 key expansion rounds; and

an execution unit coupled with the decode unit, and coupled with the plurality of the packed data registers, the execution unit, in response to the decode of the instruction, to store a 128-bit result packed data in the destination packed data register, the 128-bit result packed data to include four 32-bit round keys for four immediately subsequent and sequential SM4 key expansion rounds.

27. The processor of claim 26, in which the four 32-bit round keys for four prior SM4 key expansion rounds are to be arranged according to round order.

28. The processor of claim 27, in which the four 32-bit key generation constants for the four prior SM4 key expansion rounds are to be arranged according to round order.

29. The processor of claim 26, in which the four 32-bit round keys for four prior SM4 key expansion rounds and the four 32-bit key generation constants for corresponding rounds are to be stored in corresponding data element positions of the first and second 128-bit source packed data.

30. The processor of claim 26, in which the decode unit is to decode the instruction that is to have one or more bits to flexibly specify that the four immediately subsequent and sequential SM4 key expansion rounds are key expansion rounds instead of cipher rounds.