Glitch detection and method for detecting a glitch

• US 10,015,609 B2
• Filed: 06/05/2017
• Issued: 07/03/2018
• Est. Priority Date: 11/17/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kropfitsch, Michael, Ceballos, Jose Luis
• Primary Examiner(s): Mei, Xu
• Application Number:
  US15/614,399
• Publication Number:
  US 20170272879A1
• Time in Patent Office: 393 Days
• Field of Search: 327 33- 34, 327 77- 78, 381107, 381111-115, 381120, 381123, 381174, 381 58, 381 91, 381 92, 381122, 330199
• CPC Class Codes: H04R 19/005 using semiconductor materials
• CPC Class Codes: H04R 19/016 for microphones
• CPC Class Codes: H04R 19/04 Microphones H04R19/01 takes precedence
• CPC Class Codes: H04R 2201/003 Mems transducers or their use of the electrostatic type H04R19/005
• CPC Class Codes: H04R 29/004 for microphones H04R29/007 takes precedence
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones
• CPC Class Codes: H04R 3/007 Protection circuits for transducers

Abstract

System and method for detecting a glitch is disclosed. An embodiment comprises increasing a bias voltage of a first capacitor, sampling an input signal of a first plate of the first capacitor with a time period, mixing the input signal with the sampled input signal, and comparing the mixed signal with a reference signal.

Claims

1. A circuit comprising:

a glitch detection circuit comprising a comparator coupled to an input of the glitch detection circuit, the glitch detection circuit configured to detect a signal glitch at the input of the glitch detection circuit and produce a glitch detection signal at an output of the glitch detection circuit via the comparator when the signal glitch is detected; and

a switch having a controllable conductive path configured to be electrically connected between a first terminal configured to be coupled to a MEMS transducer and the comparator of the glitch detection circuit, wherein the switch is configured to connect the first terminal to the comparator of the glitch detection circuit when the switch is on, and is configured to disconnect the first terminal from the comparator of the glitch detection circuit when the switch is off.

2. The circuit according to claim 1, wherein the glitch detection circuit further comprises a switched capacitor circuit.

3. The circuit according to claim 1, wherein the switch is electrically connected to ground via a first resistor.

4. The circuit according to claim 3, further comprising a second resistor coupled to the switch, and wherein the first resistor has a resistance between 100 kΩ

and 10 MΩ

, and the second resistor has resistance of greater than 1 GΩ

.

5. The circuit of claim 1, wherein the glitch detection circuit comprises:

a first summer configured to

calculate an output signal,

receive an input signal from the input to the glitch detection circuit,

receive a sampled input signal, the sampled input signal being based on the input signal, and

subtract the sampled input signal from the received input signal to form an output signal; and

the comparator is configured to generate the glitch detection signal by comparing the calculated output signal with a reference signal.

6. A method of operating a circuit, the method comprising:

electrically connecting a signal node of a first system to a comparator of a glitch detection circuit using a switch during a first mode, the first system comprising a first capacitor having a capacitance proportional to a pressure level;

detecting a signal glitch on the signal node of the first system using the glitch detection circuit;

using the comparator, generating a glitch detection signal at an output of the glitch detection circuit based on the detecting; and

electrically disconnecting the signal node of the first system from the comparator of the glitch detection circuit using the switch during a second mode.

7. The method of claim 6, wherein the first mode comprises a calibration mode and the second mode comprises a normal operation mode.

8. The method of claim 7, wherein the calibration mode comprises:

increasing a bias voltage of the first capacitor;

sampling an input signal of a first plate of the first capacitor with a time period;

calculating an output signal from the sampled input signal and the input signal; and

comparing the calculated output signal with a reference signal.

9. The method of claim 6, further comprising electrically connecting the first capacitor to ground via a first resistor using the switch during the first mode.

10. The method of claim 6, further comprising:

generating a signal at the signal node using a MEMS transducer; and

amplifying the signal using an amplifier of the glitch detection circuit coupled between the signal node and the comparator, wherein the switch is connected between the signal node and an input of the amplifier.

11. The method of claim 6, further comprising:

receiving an input signal from signal node of the first system to form a received signal;

sampling the received input signal to form a sample signal;

subtract the sampled signal from the received signal to form an output signal; and

using the comparator, comparing the output signal with a reference signal to form the glitch detection signal.

12. A circuit comprising:

a first plate terminal configured to be coupled to a first plate of a first capacitor;

a second plate terminal configured to be coupled to a second plate of the first capacitor;

a first circuit comprising

an amplifier configured to be coupled to the first plate terminal and configured to amplify an input signal from the first plate terminal, and

a charge pump circuit coupled to the second plate terminal and configured to apply a bias voltage to the first capacitor via the second plate terminal;

a switch coupled to the first plate terminal; and

a second circuit coupled to the first plate terminal through the switch, wherein the second circuit comprises

a sampling circuit coupled to the first plate terminal via the switch and configured to generate a sampled signal by sampling the input signal with a sampling time period when the switch is conducting,

a subtractor coupled to the first plate terminal via the switch and coupled to the sampling circuit, wherein the subtractor is configured to generate a subtracted signal by subtracting the sampled signal from the input signal when the switch is conducting,

a reference circuit configured to generate a reference signal, and

a comparator coupled to the reference circuit and the subtractor, wherein the comparator is configured to compare the reference signal with the subtracted signal.

13. The circuit of claim 12, wherein the first plate of the first capacitor comprises a backplate of a microelectromechanical systems (MEMS) microphone and a second plate of the first capacitor comprises a membrane of the MEMS microphone.

14. The circuit of claim 12, wherein the sampling circuit comprises a switched sampling capacitor.

15. The circuit of claim 14, wherein the sampling circuit further comprises

a first buffer coupled to an input of the switched sampling capacitor, and

a second buffer coupled to an output of the switched sampling capacitor.

16. The circuit of claim 12, wherein the second circuit comprises a glitch detection circuit configured to detect a glitch and an output of the comparator indicates an absence or presence of a detected glitch.

17. The circuit of claim 16, wherein the charge pump circuit is configured to increase the bias voltage until the glitch detection circuit detects a glitch.

18. The circuit of claim 16, wherein a glitch occurs with a glitch time period, and wherein the sampling time period is shorter than the glitch time period.