Vmin retention detector apparatus and method

• US 10,018,674 B2
• Filed: 03/16/2016
• Issued: 07/10/2018
• Est. Priority Date: 03/16/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Honkote, Vinayak, Vangal, Sriram R.
• Primary Examiner(s): NGUYEN, THIEN DANG
• Application Number:
  US15/072,280
• Publication Number:
  US 20170269155A1
• Time in Patent Office: 846 Days
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3173 Marginal testing
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.

Claims

1. An apparatus comprising:

a state detector comprising state retention circuits, wherein the state detector is to receive a clock, wherein the state detector is operable to detect logic states of zero and one of the state retention circuits in response to a clock edge of the clock; and

an error detector coupled to the state detector, wherein the error detector is to receive the detected logic states of the state retention circuits, and wherein the error detector is to detect an error in the detected logic states,

wherein the state retention circuits comprise a first sequential logic and a second sequential logic, wherein the first sequential logic is to store a first expected logic state, and wherein the second sequential logic is to store a second expected logic state, wherein the first expected logic state is different from the second expected logic state.

2. The apparatus of claim 1 comprises a power management unit (PMU) to receive an output of the error detector and to adjust a power supply level according to the output of the error detector.

3. The apparatus of claim 2 comprises a voltage regulator coupled to the PMU, wherein the voltage regulator is to adjust the power supply level according to an instruction from the PMU.

4. The apparatus of claim 1, wherein the first sequential logic comprises a data input coupled to a supply node to store the first expected logic state;

and wherein the second sequential logic comprises a data input coupled to a ground node to store the second expected logic state, and wherein clock inputs of the first and second sequential logics are coupled together and are to receive the clock edge.

5. The apparatus of claim 4, wherein at least one of the first and second sequential logics comprise a tunable load coupled to one of one or more nodes of the first and second sequential logics.

6. The apparatus of claim 5, wherein the tunable load comprises one or more switching devices coupled to one or more capacitive loads.

7. The apparatus of claim 4, wherein the first and second sequential logics include active or passive devices with highest voltage threshold and smallest size as available by a process technology on which they are based.

8. The apparatus of claim 4, wherein the error detector comprises:

a first compare logic coupled to an output node of the first sequential unit, wherein the first compare logic is to compare an output on the output node to a voltage on the supply node; and

a second compare logic coupled to an output node of the second sequential unit, wherein the second compare logic is to compare an output on the output node of the second sequential unit to a voltage on the ground node.

9. The apparatus of claim 8, wherein the error detector comprises a merge logic to merge outputs of the first and second compare logic.

10. The apparatus of claim 9, comprises a power management unit (PMU) to which is to receive an output of the merge logic.

11. A system comprising:

a memory;

a processor coupled to the memory, the processor having a V_min detector which comprises;

a state detector comprising state retention circuits, wherein the state detector is to receive a clock, wherein the state detector is operable to detect logic states of zero and one of the state retention circuits in response to a clock edge of the clock; and

an error detector coupled to the state detector, wherein the error detector is to receive the detected logic states of the state retention circuits, and wherein the error detector is to detect an error in the detected logic states;

wherein the state retention circuits comprise a first sequential logic and a second sequential logic, wherein the first sequential logic is to store a first expected logic state, wherein the second sequential logic is to store a second expected logic state, and wherein the first expected logic state is different from the second expected logic state, and

a wireless interface to allow the processor to communicate with another device.

12. The system of claim 11, wherein the processor comprises a power management unit which is communicatively coupled to the error detector.

13. The system of claim 11, wherein the processor comprises a voltage regulator which is operable to adjust a power supply level according to the detected error.

14. The system of claim 11, wherein the first sequential logic having comprises a data input coupled to a supply node to store the first expected logic state;

wherein the second sequential logic comprises a data input coupled to a ground node to store the second expected logic state, and wherein clock inputs of the first and second sequential logics are coupled together and are to receive the clock edge.