Processor for a radio receiver

• US 10,018,731 B2
• Filed: 01/15/2015
• Issued: 07/10/2018
• Est. Priority Date: 01/16/2014
• Status: Active Grant

• Current Assignee: Qinetiq Limited (QinetiQ Group PLC)
• Original Assignee: Qinetiq Limited (QinetiQ Group PLC)
• Inventors: MacLeod, Malcolm
• Primary Examiner(s): Liu, Harry K
• Application Number:
  US15/111,042
• Publication Number:
  US 20160327652A1
• Time in Patent Office: 1,272 Days
• Field of Search: 34235769
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence

Abstract

A processor for a radio receiver is adapted to process direct sequence spread spectrum (DS-SS signals), and includes a demodulator, digitizer, correlator, and chip-matched filter (CMF) wherein the digitizer sample rate is selected to take a plurality of samples of each incoming chip at differing points thereon compared to sample points on an adjacent chip and to sample the chip at a non-integer multiple of the chip rate, wherein the CMF is arranged to filter the output of the digitizer. A sample selection unit is arranged to select a single sample from the CMF for input to each tap of the correlator, the selected sample being chosen as that nearest in time to a desired ideal time in relation to a timing reference point on the chip. An improved correlation function results, leading to better tracking performance.

Claims

1. A processor system for a radio receiver, the processor system being adapted to process Direct Sequence Spread Spectrum (DS-SS) signals, said processor system having a demodulator, the demodulator comprising of a digitiser for digitising a received signal at a predetermined sample rate, said received signal comprising of a sequence of chips arriving at the processor at a known rate;

and at least one correlator for correlating the digitised signal with a known signal, the correlator being arranged to have one tap per chip;

the digitiser being arranged to take a plurality of samples of each chip, at differing points thereon as compared to the sample points on an adjacent chip, and to have a sample rate that is not an integer multiple of the chip rate;

wherein the processor further incorporates a chip-matched filter (CMF) arranged to filter the output of the digitiser, and a sample selection unit (SSU) arranged to receive outputs from the CMF and to select, for input to each tap of the correlator, the CMF output nearest in time to a desired ideal time in relation to a timing reference point on the chip.

2. A processor as claimed in claim 1 wherein the chip-matched filter is matched to a predetermined chip waveform expected at the processor.

3. A processor as claimed in claim 1 wherein the average number of samples per chip taken by the digitiser is at least 2.

4. A processor as claimed in claim 3 wherein the average number of samples per chip taken by the digitiser is at least 8.

5. A processor as claimed in claim 1 wherein the timing reference point is taken with reference to an internal clock system.

6. A processor as claimed in claim 1 wherein the processor has a plurality of correlators arranged in pairs, with a first correlator in a given pair being adapted to have a first desired ideal time at a first point with reference to the timing reference point, and the second correlator in the pair adapted to have a second desired ideal time at a second point with reference to the timing reference point.

7. A processor as claimed in claim 6 wherein the temporal separation between the first and second desired ideal times is set at a quarter of a chip duration.

8. A processor as claimed in claim 6 wherein outputs from the first and second correlators are combined into a single output.

9. A processor as claimed in claim 6, wherein the processor is used to process Binary Offset Carrier (BOC) signals.

10. A processor as claimed in claim 1 wherein the processor is used in the processing of signals from a Global Navigation Satellite System (GNSS).

11. A receiver incorporating a processor according to claim 1.

12. A receiver as claimed in claim 11 wherein said receiver has a front end adapted to provide a down-converted signal to the processor.

13. A method of processing a direct sequence-spread spectrum (DS-SS) signal comprising a sequence of chips received in a receiver, said chips being received at a known rate, the method comprising the steps of:

a) digitising the signal at a sample rate at least twice the chip rate, wherein the sample rate is a non-integer multiple of the chip rate, such that successive chips are sampled at different points thereon;

b) filtering the samples with a chip-matched filter (CMF), wherein the chip matched filter is substantially matched to the expected chip shape, the CMF providing an output sample for each input sample;

c) selecting a single output of the CMF for each chip for input to a correlator;

d) correlating the inputs provided by selection step c) with a reference signal;

wherein the single output from the CMF nearest to an ideal desired timing point for each chip is chosen for input to the correlator.

14. A method as claimed in claim 13 further comprising the steps of:

e) for each chip, selecting a second output from the CMF nearest in time to a second desired ideal timing point, and providing the output to a second correlator;

f) correlating the selected outputs with the reference signal in the correlator;

g) combining the outputs of the two correlators to produce a single output.