Time critical tasks scheduling

• US 10,019,286 B2
• Filed: 05/27/2016
• Issued: 07/10/2018
• Est. Priority Date: 04/09/2013
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Chandhoke, Sundeep, Salmon, IV, Herbert K.
• Primary Examiner(s): Kim, Dong
• Application Number:
  US15/167,638
• Publication Number:
  US 20160274939A1
• Time in Patent Office: 774 Days
• Field of Search: None
• CPC Class Codes: G06F 2209/486 Scheduler internals
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day
• CPC Class Codes: G06F 9/4887 involving deadlines, e.g. rate based, periodic

Abstract

A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task.

Claims

1. An apparatus for scheduling a time critical task, the apparatus comprising:

a hardware assist scheduler; and

a memory coupled to the hardware assist scheduler;

wherein the apparatus is configured to;

determine a schedule for the time critical task based on received timing information, wherein the schedule comprises a wakeup time, a specified thread bandwidth and an overall thread deadline, wherein the time critical task executes program instructions via a thread on a core of the processing unit in accordance with the schedule, and wherein the processing unit is configured to communicate with the memory and the hardware assist scheduler; and

suspend execution of the time critical task via assertion of a thread interrupt in response to a lateness timer expiring, wherein the lateness timer is based on the wakeup time.

2. The apparatus of claim 1,

wherein the time critical task is a function of the overall thread deadline and the specified thread bandwidth.

3. The apparatus of claim 1,

wherein the apparatus is further configured to:

notify the processing unit that the thread is in an idle state, wherein the idle state indicates that the thread is awake and ready to resume execution and execute the time critical task in accordance with the schedule.

4. The apparatus of claim 3,

wherein to notify the processing unit, the apparatus is further configured to:

perform a memory write to a memory monitored by the processing unit.

5. The apparatus of claim 1,

wherein the overall thread deadline is based on the difference between the thread cycle time and a system dependent suspend latency.

6. The apparatus of claim 1,

wherein to determine the schedule, the apparatus is further configured to:

determine a wakeup time, a thread cycle time, and an overall thread deadline.

7. The apparatus of claim 1,

wherein the thread comprises a multiplexed thread, wherein the multiplexed thread is executed on the core of the processing unit, and wherein the multiplexed thread comprises:

one or more time critical tasks; and

a best effort task.

8. A non-transitory computer readable memory medium storing program instructions executable by at least one processor to:

determine a schedule for a time critical task based on received timing information, wherein the schedule comprises a wakeup time, a specified thread bandwidth and an overall thread deadline, wherein the time critical task executes program instructions via a thread on a core of a processing unit in accordance with the schedule; and

suspend execution of the time critical task via assertion of a thread interrupt in response to a lateness timer expiring, wherein the lateness timer is based on the wakeup time.

9. The non-transitory computer readable memory medium of claim 8,

wherein the time critical task is a function of the overall thread deadline and the specified thread bandwidth.

10. The non-transitory computer readable memory medium of claim 8,

wherein the program instructions are further executable to:

notify the processing unit that the thread is in an idle state, wherein the idle state indicates that the thread is awake and ready to resume execution and execute the time critical task in accordance with the schedule.

11. The non-transitory computer readable memory medium of claim 10,

wherein to notify the processing unit, the program instructions are further executable to:

perform a memory write to a memory monitored by the processing unit.

12. The non-transitory computer readable memory medium of claim 8,

wherein the overall thread deadline is based on the difference between the thread cycle time and a system dependent suspend latency.

13. The non-transitory computer readable memory medium of claim 8,

wherein to determine the schedule, the program instructions are further executable to:

determine a wakeup time, a thread cycle time, and an overall thread deadline.

14. The non-transitory computer readable memory medium of claim 8,

wherein the thread comprises a multiplexed thread, wherein the multiplexed thread is executed on the core of the processing unit, and wherein the multiplexed thread comprises:

one or more time critical tasks; and

a best effort task.

15. A method for monitoring a time critical task, the method comprising:

determining a schedule for the time critical task based on received timing information, wherein the schedule comprises a wakeup time, a specified thread bandwidth and an overall thread deadline, wherein the time critical task executes program instructions via a thread on a core of a processing unit in accordance with the schedule; and

suspending execution of the time critical task via assertion of a thread interrupt in response to a lateness timer expiring, wherein the lateness timer is based on the wakeup time.

16. The method of claim 15,

wherein the time critical task is a function of the overall thread deadline and specified thread bandwidth.

17. The method of claim 15, further comprising:

notifying the processing unit that the thread is in an idle state, wherein the idle state indicates that the thread is awake and ready to resume execution and execute the time critical task in accordance with the schedule.

18. The method of claim 15,

wherein the overall thread deadline is based on the difference between the thread cycle time and a system dependent suspend latency.

19. The method of claim 15,

wherein determining the schedule comprises:

determining a wakeup time, a thread cycle time, and an overall thread deadline.

20. The method of claim 15,

wherein the thread comprises a multiplexed thread, wherein the multiplexed thread is executed on the core of the processing unit, and wherein the multiplexed thread comprises:

one or more time critical tasks; and

a best effort task.