Live error recovery

• US 10,019,300 B2
• Filed: 02/12/2016
• Issued: 07/10/2018
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jayaprakash Bharadwaj, Prahladachar, Brown, Alexander, Das Sharma, Debendra, Thaliyil, Junaid
• Primary Examiner(s): NGUYEN, THIEN DANG
• Application Number:
  US15/042,463
• Publication Number:
  US 20160335148A1
• Time in Patent Office: 879 Days
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1415 at system level
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

Claims

1. An apparatus comprising:

a receiver to receive a packet at a particular port of a serial data link;

error logic comprising circuitry to;

determine that the packet is associated with an uncorrectable error;

determine, from one or more bits in a capability register, that a particular error containment mode is enabled for the particular port;

initiate entry into the particular error containment mode based on the determination that the packet is associated with the error and the determination that the particular error containment mode is enabled, wherein entry into the particular error containment mode is to cause traffic on the serial data link to be halted downstream from the port without a system-wide reset; and

send a signal to identify the uncorrectable error as a correctable error based on entry into the particular error containment mode.

2. The apparatus of claim 1, wherein forcing the serial data link down causes all subsequent inbound packets to be dropped.

3. The apparatus of claim 2, wherein forcing the serial data link down further causes all pending outbound requests and completions to be aborted.

4. The apparatus of claim 3, wherein the error logic is further to generate and send a master abort completion for one of the completions caused to be aborted.

5. The apparatus of claim 1, wherein the error logic is further to drop the packet.

6. The apparatus of claim 1, wherein the error is at least one of a group comprising:

a transaction layer packet error, a flow control protocol error, and a data link layer protocol error.

7. The apparatus of claim 1, wherein the error logic is further to determine that the uncorrectable error is one of a set of errors that is to trigger the live error recovery mode.

8. The apparatus of claim 7, wherein the set of errors is identifiable from an error mask register corresponding to the live error recovery mode.

9. The apparatus of claim 8, wherein the set of errors is further included in errors identified as uncorrectable errors by a particular error mask.

10. The apparatus of claim 1, wherein entering the live error recovery mode includes entering a disable state.

11. The apparatus of claim 1, wherein the error logic is further to force association of the uncorrectable error with a correctable severity.

12. The apparatus of claim 11, wherein the error logic is further to cause the uncorrectable error to be corrected.

13. The apparatus of claim 1, wherein the error logic is further to identify that all transactions on the serial data link have been dropped and identify that all error registers for the serial data link have been cleared.

14. The apparatus of claim 13, wherein the error logic is to determine that the transactions have been dropped based on a quiesced control bit value of a register.

15. The apparatus of claim 13, wherein the error logic is to clear an error recovery bit of a status control register corresponding to the serial data link based on identifying that all transactions on the serial data link have been dropped and that all error registers for the serial data link have been cleared.

16. The apparatus of claim 15, wherein the error logic is further to initiate retraining of the serial data link based on the clearing of the error recovery bit, wherein the error recovery bit indicates whether live error recovery mode is active.

17. The apparatus of claim 1, wherein the error logic is further to determine a type of the uncorrectable error, and the signal to identify the uncorrectable error as a correctable error is to be sent based at least in part on the type of the uncorrectable error.

18. An apparatus comprising:

an agent to support communication on a serial data link;

a memory comprising a capability register;

a receiver to receive a packet;

error logic comprising circuitry to;

determine that the packet is associated with an uncorrectable error;

determine, from one or more bits in the capability register, that a particular error containment mode is enabled for the particular port; and

initiate entry into the particular error containment mode based on the determination that the packet is associated with the error and the determination that the particular error containment mode is enabled, wherein entry into the particular error containment mode is to cause interface logic to drop an inbound packet and abort an outbound request; and

a transmitter to send a signal to identify the uncorrectable error as a correctable error based on entry into the particular error containment mode.

19. A system comprising:

a first device;

a second device to be communicatively coupled to the first device over an interconnect, the second device comprising error logic executable to;

identify a packet at a port coupled to a serial data link of the interconnect;

determine that the packet is associated with an uncorrectable error;

determine, from one or more bits in a capability register, that a particular error containment mode is enabled for the particular port;

initiate the particular error containment mode on the port based on the determination that the packet is associated with the uncorrectable error and the determination that the particular error containment mode is enabled, wherein the particular error containment mode is to contain the error to the port by disabling the serial data link downstream from the port; and

send a signal to identify the uncorrectable error as a correctable error based on entry into the particular error containment mode.

20. The system of claim 19, wherein the interconnect is compliant with a Peripheral Component Interconnect Express (PCle) based interconnect protocol.