Validation of a symbol response memory

• US 10,019,311 B2
• Filed: 09/29/2016
• Issued: 07/10/2018
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Natural Intelligence Systems, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noyes, Harold B, Brown, David R., Glendenning, Paul
• Primary Examiner(s): Rizk, Sam
• Application Number:
  US15/280,481
• Publication Number:
  US 20180089019A1
• Time in Patent Office: 649 Days
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

Claims

1. A device, comprising:

a plurality of blocks, each block of the plurality of blocks comprising a plurality of rows, each row of the plurality of rows comprising a plurality of configurable elements, each configurable element of the plurality of configurable elements comprising a data analysis element comprising a memory component programmed with configuration data, wherein the data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis; and

an error detection engine (EDE) configured to perform integrity validation of the configuration data.

2. The device of claim 1, wherein the EDE is configured to perform integrity validation of the configuration data at least partially by performing one or more cyclic redundancy checks (CRC).

3. The device of claim 2, wherein the EDE is configured to perform the one or more CRCs at least partially by:

receiving the configuration data from a host processor each time the host processor programs the memory component of the data analysis element included in each of the plurality of configurable elements;

calculating one or more initial CRC values based on the configuration data; and

storing the one or more initial CRC values in a memory of the CRC engine.

4. The device of claim 2, wherein the EDE is configured to perform the one or more CRCs at least partially by:

receiving one or more initial CRC values calculated by a host processor based on the configuration data each time the host processor programs the memory component of the data analysis element included in each of the plurality of configurable elements; and

storing the one or more initial CRC values in a memory of the CRC engine.

5. The device of claim 4, wherein the EDE is configured to perform the one or more CRCs at least partially by:

receiving an instruction to perform the one or more CRCs from the host processor.

6. The device of claim 5, wherein the EDE is configured to perform the one or more CRCs at least partially by:

retrieving the one or more initial CRC values;

retrieving the configuration data stored in the memory component of the data analysis element included in each of the plurality of configurable elements;

calculating one or more subsequent CRC values based on the retrieved configuration data;

comparing the one or more subsequent CRC values to the one or more initial CRC values; and

outputting a signal to the host processor when the one or more subsequent CRC values differ from the one or more initial CRC values.

7. The device of claim 6, wherein the EDE is configured to retrieve the configuration data by requesting the configuration data from a symbol response memory (SRM).

8. The device of claim 6, wherein the EDE is configured to retrieve the configuration data by reading the configuration data directly from the memory component.

9. The device of claim 6, wherein the host processor, based on the signal, is configured to reprogram the memory component of the data analysis element of each of the plurality of configuration elements with the configuration data.

10. The device of claim 1, wherein the EDE is configured to perform the integrity validation at the block level, at a core level including the plurality of blocks, or both.

11. The device of claim 1, wherein the memory component comprises a symbol response memory (SRM) including a plurality of memory cells that each store a high value or a low value based on the configuration data.

12. A device, comprising:

a state machine engine comprising;

a plurality of blocks, each block of the plurality of blocks comprising;

a plurality of rows, each row of the plurality of rows comprising;

a plurality of configurable elements, each configurable element of the plurality of configurable elements configured to be programmed via configuration data to analyze at least a portion of a data stream and to selectively output the result of the analysis; and

one or more data locations storing the configuration data; and

an error detection engine (EDE) configured to validate the integrity of the configuration data of the one or more data locations.

13. The device of claim 12, wherein the state machine engine includes a finite state machine lattice comprising the plurality of blocks and the EDE.

14. The device of claim 13, wherein the device comprises a host processor and the finite state machine lattice comprises a programming interface that is configured to:

receive the configuration data from the host processor;

program each of the plurality of configurable elements with the configuration data; and

send the configuration data to the EDE to calculate one or more initial cyclic redundancy check (CRC) values based on the configuration data each time the configuration data is received from the host processor.

15. The device of claim 12, wherein the EDE is configured to validate the integrity of the configuration data at least partially by performing a cyclic redundancy check (CRC), wherein performing the CRC comprises:

receiving the configuration data from a host processor of the device each time the host processor programs each of the plurality of configurable elements;

calculating one or more initial CRC values based on the configuration data;

receiving an instruction from the host processor to validate the integrity of the configuration data;

calculating one or more subsequent CRC values based on the configuration data retrieved at a later time; and

determining whether the one or more initial CRC values differ from the one or more subsequent CRC values.

16. The device of claim 15, wherein the EDE is configured to output a signal indicative of an error in the configuration data to the host processor when the one or more initial CRC values differ from the one or more subsequent CRC values.

17. The device of claim 16, wherein the host processor is configured to reprogram each of the plurality of configurable elements based on the signal.

18. The device of claim 12, wherein the EDE is configured to validate the integrity of the configuration data at least partially by:

receiving one or more initial cyclic redundancy check (CRC) values from a host processor of the device;

receiving an instruction from the host processor to validate the integrity of the configuration data;

calculating one or more subsequent CRC values based on the configuration data retrieved at a later time; and

determining whether the one or more initial CRC values differs from the one or more subsequent CRC values.

19. The device of claim 12, wherein the EDE is configured to validate the integrity of the configuration data at least partially by determining whether an initial cyclic redundancy check (CRC) value generated based on the configuration data at a first time differs from a subsequent CRC value generated at a second time.

20. A device, comprising:

a finite state machine lattice comprising;

a plurality of blocks, each block of the plurality of blocks comprising;

a plurality of rows, each row of the plurality of rows comprising;

a plurality of configurable elements, each configurable element of the plurality of configurable elements comprising a symbol response memory (SRM) that stores configuration data used to analyze at least a portion of a data stream and to selectively output the result of the analysis; and

an error detection engine (EDE) configured to validate the integrity of the configuration data at least partially by determining whether an initial cyclic redundancy check (CRC) value generated based on the configuration data at a first time differs from a subsequent CRC value generated at a second time.

21. The device of claim 20, wherein the EDE is configured to output a signal indicative of an error to a host processor of the device when the initial CRC value differs from the subsequent CRC value.

22. The device of claim 21, wherein the host processor is configured to reprogram each of the plurality of configurable elements based on the signal.

23. A method, comprising:

calculating one or more initial cyclic redundancy check (CRC) values at a first time based on configuration data stored in one or more memory components included in a state machine engine used to analyze at least a portion of a data stream and to selectively output the result of the analysis;

receiving an instruction to validate the configuration data stored in the one or more memory components;

calculating one or more subsequent CRC values at a second time based on the configuration data stored in the one or more memory components of the state machine engine used to analyze at least the portion of the data stream;

determining whether the one or more subsequent CRC values differ from the one or more initial CRC values; and

performing a corrective action when the one or more subsequent CRC values differ from the one or more initial CRC values.

24. The method of claim 23, wherein performing the corrective action comprises altering at least one of a plurality of memory cells included in a symbol response memory (SRM), wherein at least one of the one or more memory components comprises the SRM.

25. The method of claim 23, comprising reading the configuration data from each memory cell included in the one or more memory components, reading the configuration data from a vector included in the one or more memory components, or reading the configuration data from a register included in the one or more memory components at the second time.