Flash memory apparatus and storage management method for flash memory
First Claim
1. A flash memory apparatus, comprising:
- a flash memory module comprising a plurality of storage blocks, each storage block can be used as a first block or a second block; and
a flash memory controller, configured for classifying data to be programmed into a plurality of groups of data, respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks, a cell of the first blocks being arranged for storing data of 1 bit;
wherein the flash memory controller is further arranged for reading out the groups of data from the first blocks, executing error correction and de-randomize operation upon read out data to generate de-randomized data, executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data, performing error code encoding upon the randomized data to generate a second corresponding parity check code, storing the randomized data and the second corresponding parity check code into the flash memory module as the second block, a cell of the second block being arranged for storing data of at least 2 bits.
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Accused Products
Abstract
A method used for a flash memory module having a plurality of storage blocks each can be used as a first block or a second block includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks; reading out the groups of data from the first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon the randomized data to generate a second corresponding parity check code; and storing the randomized data and the second corresponding parity check code into the flash memory module as the second block.
125 Citations
7 Claims
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1. A flash memory apparatus, comprising:
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a flash memory module comprising a plurality of storage blocks, each storage block can be used as a first block or a second block; and a flash memory controller, configured for classifying data to be programmed into a plurality of groups of data, respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks, a cell of the first blocks being arranged for storing data of 1 bit; wherein the flash memory controller is further arranged for reading out the groups of data from the first blocks, executing error correction and de-randomize operation upon read out data to generate de-randomized data, executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data, performing error code encoding upon the randomized data to generate a second corresponding parity check code, storing the randomized data and the second corresponding parity check code into the flash memory module as the second block, a cell of the second block being arranged for storing data of at least 2 bits. - View Dependent Claims (2, 3)
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4. A flash memory storage management method used for a flash memory module having a plurality of storage blocks, each storage block can be used as a first block or a second block, and the flash memory storage management method comprises:
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classifying data to be programmed into a plurality of groups of data; respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks, a cell of the first blocks being arranged for storing data of 1 bit; reading out the groups of data from the first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon the randomized data to generate a second corresponding parity check code; and storing the randomized data and the second corresponding parity check code into the flash memory module as the second block, a cell of the second block being arranged for storing data of at least 2 bits. - View Dependent Claims (5)
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6. A flash memory controller connected to a flash memory module having a plurality of storage blocks, each storage block can be used as a first block or a second block, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks, and the flash memory controller comprises:
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a decoding circuit, configured for executing error correction upon read out data which is read out by the flash memory controller from the first blocks; a de-randomizer, coupled to the decoding circuit, configured for performing a de-randomize operation upon the read out data to generate de-randomized data; a randomizer, coupled to the de-randomizer, configured for executing a randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; and an encoding circuit, coupled to the randomizer, configured for performing the error code encoding upon the randomized data to generate a second corresponding parity check code; wherein the flash memory controller is arranged for storing the randomized data and the second corresponding parity check code into the flash memory module as the second block, a cell of the first blocks being arranged for storing data of 1 bit, a cell of the second block being arranged for storing data of at least 2 bits. - View Dependent Claims (7)
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Specification