Flash memory apparatus and storage management method for flash memory

• US 10,019,355 B2
• Filed: 01/01/2018
• Issued: 07/10/2018
• Est. Priority Date: 04/27/2016
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Inventors: Yang, Tsung-Chieh, Hsu, Hong-Jung
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/859,724
• Publication Number:
  US 20180121347A1
• Time in Patent Office: 190 Days
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Claims

1. A flash memory apparatus, comprising:

a flash memory module comprising a plurality of first blocks and at least one second block; and

a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks, a cell of the plurality of first blocks being arranged for storing data of two bits;

wherein after completing program of the plurality of first blocks, the flash memory module is arranged for performing an internal copy operation to program the at least one second block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of first blocks to the at least one second block, a cell of the second block being arranged for storing data of 2^N bits, N being an integer equal to 2 or greater than 2.

2. The flash memory apparatus of claim 1, wherein N is equal to 3, and the at least one second block is a triple-level-cell block, and the flash memory controller is arranged for classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks.

3. The flash memory apparatus of claim 1, wherein the plurality of first blocks are a plurality of single-level-cell (SLC) blocks, when programming a group of data to a single-level-cell block, the flash memory controller is arranged for sequentially organizing and classifying every (M) word lines of all word lines of the single-level-cell block as a group of word lines to generate a plurality of odd groups of word lines and a plurality of even groups of word lines, for respectively executing different (M) exclusive-OR encoding operations upon each word line within an odd group of word lines and each word line within an even group of word lines to generate (M) partial parity check codes of the each word line within the odd group of word lines and (M) partial parity check codes of the each word line within the even group of word lines, for programming and storing (M) partial parity check codes of each word line within the plurality of odd group of word lines to last data pages of last (M) word lines in the plurality of odd group of word lines, and for programming and storing (M) partial parity check codes of each word line within the plurality of even group of word lines to last data pages of last (M) word lines in the plurality of even group of word lines.

4. The flash memory apparatus of claim 1, wherein when performing memory garbage collection, the flash memory controller is arranged for externally reading out and retrieving data from the plurality of first blocks or from the at least one second block for re-encoding and re-programming the read out and retrieved data.

5. The flash memory apparatus of claim 1, wherein when programming data into the at least one second block and shutdown occurring, the flash memory module is arranged to discard data stored by the at least one second block and perform the internal copy operation to copy and program data from the plurality of first blocks into the at least one second block.

6. The flash memory apparatus of claim 1, wherein when programming data into the plurality of first blocks, the flash memory controller is arranged to program data into the plurality of first blocks according to a randomizer seed rule of the at least one second block.

7. A flash memory storage management method used in a flash memory module having a plurality of first blocks and at least one second block, comprising:

classifying data to be programmed into a plurality of groups of data;

respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks, a cell of the plurality of first blocks being arranged for storing data of two bits; and

controlling the flash memory module to perform an internal copy operation to program the at least one second block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of first blocks to the at least one second block, a cell of the second block being arranged for storing data of 2^N bits, N being an integer equal to 2 or greater than 2.

8. The method of claim 7, wherein N is equal to 3, and the at least one second block is a triple-level-cell block, and the step of classifying the data to be programmed into N groups of data comprises:

classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks.

9. The method of claim 7, wherein the plurality of first blocks are a plurality of single-level-cell (SLC) blocks, and the executing step comprises:

when programming a group of data to a single-level-cell block, sequentially organizing and classifying every (M) word lines of all word lines of the single-level-cell block as a group of word lines to generate a plurality of odd groups of word lines and a plurality of even groups of word lines;

respectively executing different (M) exclusive-OR encoding operations upon each word line within an odd group of word lines and upon each word line within an even group of word lines to generate (M) partial parity check codes of the each word line within the odd group of word lines and (M) partial parity check codes of the each word line within the even group of word lines; and

programming and storing (M) partial parity check codes of each word line within the plurality of odd group of word lines to last data pages of last (M) word lines in the plurality of odd group of word lines, and for programming and storing (M) partial parity check codes of each word line within the plurality of even group of word lines to last data pages of last (M) word lines in the plurality of even group of word lines.

10. The method of claim 7, further comprising:

when performing memory garbage collection, reading out and retrieving data from the plurality of first blocks or from the at least one second block for re-encoding and re-programming the read out and retrieved data.

11. The method of claim 7, further comprising:

when programming data into the at least one second block and shutdown occurring, discarding data stored by the at least one second block and performing the internal copy operation to copy and program data from the plurality of first blocks into the at least one second block.

12. The method of claim 7, further comprising:

when programming data into the plurality of first blocks, programming data into the plurality of first blocks according to a randomizer seed rule of the at least one second block.

13. A flash memory controller, comprising:

a plurality of channels respectively connected to a flash memory module having a plurality of first blocks and at least one second block; and

an error correction code encoding circuit;

wherein the flash memory controller is configured for classifying data to be programmed into a plurality of groups of data, using the error correction code encoding circuit to respectively execute single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks, a cell of the plurality of first blocks being arranged for storing data of two bits;

after completing program of the plurality of first blocks, the flash controller controls the flash memory module to perform an internal copy operation to program the at least one second block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of first blocks to the at least one second block, a cell of the second block being arranged for storing data of 2^N bits, N being an integer equal to 2 or greater than 2.