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Satisfying memory ordering requirements between partial reads and non-snoop accesses

  • US 10,019,366 B2
  • Filed: 07/11/2017
  • Issued: 07/10/2018
  • Est. Priority Date: 07/07/2008
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a controller to interface between at least a first processor to recognize a first instruction set and second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising interface logic to couple to a link comprising a plurality of lanes;

    the interface logic to;

    receive a snoop invalidate message, wherein the snoop invalidate message corresponds to a particular cache line; and

    send a writeback message responsive to the snoop invalidate message, wherein the writeback message is to indicate a write to a home agent associated with the particular cache line and cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state.

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