Satisfying memory ordering requirements between partial reads and non-snoop accesses

• US 10,019,366 B2
• Filed: 07/11/2017
• Issued: 07/10/2018
• Est. Priority Date: 07/07/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Beers, Robert H., Chou, Ching-Tsun, Safranek, Robert J., Vash, James
• Primary Examiner(s): Yu, Jae
• Application Number:
  US15/646,961
• Publication Number:
  US 20170308471A1
• Time in Patent Office: 364 Days
• Field of Search: 711135
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0824 Distributed directories, e.g. linked lists of caches
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management
• CPC Class Codes: H04L 67/56 Provisioning of proxy services store-and-forward switching systems in data switching networks H04L12/54
• CPC Class Codes: H04L 67/568 Storing data temporarily at an intermediate stage, e.g. caching

Abstract

A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

Claims

1. An apparatus comprising:

a controller to interface between at least a first processor to recognize a first instruction set and second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising interface logic to couple to a link comprising a plurality of lanes;

the interface logic to;

receive a snoop invalidate message, wherein the snoop invalidate message corresponds to a particular cache line; and

send a writeback message responsive to the snoop invalidate message, wherein the writeback message is to indicate a write to a home agent associated with the particular cache line and cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state.

2. A method comprising:

receiving at a particular coherency agent, a snoop invalidate message, wherein the snoop invalidate message corresponds to a partial read of a particular cache line by another coherency agent; and

generating a writeback message in response to the snoop invalidate message, wherein the writeback message is to indicate a write to a home agent associated with the particular cache line and cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state.

3. A system comprising:

cache coherent memory;

a first device comprising a first coherency agent to send a read invalidate message, wherein the read invalidate message corresponds to a particular cache line of the cache coherent memory;

a second device comprising a second coherency agent to receive a snoop invalidate message associated with the read invalidate message and generate a writeback message associated with the read invalidate message; and

a third device comprising a home agent to receive the writeback message and perform a write to the particular cache line based on the writeback message, wherein the writeback message is to cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state.

4. The system of claim 3, wherein the first device comprises a processor.

5. The system of claim 3, wherein the first device comprises an I/O device.

6. The system of claim 3, wherein the first device and second device are communicatively coupled to the third device via an interconnect comprising point-to-point links.