Memory module, computing system having the same, and method for testing tag error thereof
First Claim
1. A method of a computing system that comprises at least one nonvolatile memory, a memory module performing a cache function of the nonvolatile memory and comprising cache dynamic random access memories (DRAMs), and a processor controlling the nonvolatile memory and the memory module, the method comprising:
- outputting, at the processor, a command and an address to the memory module;
receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the cache DRAMs of the memory module, from the memory module;
determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting; and
outputting, at the processor, the determined cache hit/miss to the memory module.
1 Assignment
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Accused Products
Abstract
A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.
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Citations
20 Claims
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1. A method of a computing system that comprises at least one nonvolatile memory, a memory module performing a cache function of the nonvolatile memory and comprising cache dynamic random access memories (DRAMs), and a processor controlling the nonvolatile memory and the memory module, the method comprising:
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outputting, at the processor, a command and an address to the memory module; receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the cache DRAMs of the memory module, from the memory module; determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting; and outputting, at the processor, the determined cache hit/miss to the memory module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A tag error test method of a computing system that comprises at least one nonvolatile memory, a memory module performing a cache function of the nonvolatile memory, and a processor controlling the nonvolatile memory and the memory module, the method comprising:
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generating, at each of a plurality of cache DRAMs of the memory module, a match/unmatch bit as a result of comparing a tag corresponding to an address and a tag stored in a respective one of the plurality of cache DRAMs; determining whether a match bit count is greater than “
0” and
an unmatch bit count is greater than “
0”
; anddetermining a cache hit/miss from the match/unmatch bits through majority voting when the match bit count is greater than “
0” and
the unmatch bit count is greater than “
0”
. - View Dependent Claims (10, 11, 12, 13)
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14. A method, comprising:
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receiving a command and an address at a cache memory module, the cache memory module comprising a plurality of cache memory blocks; determining cache hit/miss information based on an input tag associated with the address and a plurality of tags stored in the plurality of cache memory blocks, respectively; determining that one of the plurality of tags is in error due to being different than other ones of the plurality of tags; determining whether the one of the plurality of tags that is different is correctable; and correcting the one of the plurality of tags that is different from the other ones of the plurality of tags at the cache memory module when the one of the plurality of tags that is different is determined to be correctable. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification