Scalable high performance 3D graphics

• US 10,019,777 B2
• Filed: 10/21/2016
• Issued: 07/10/2018
• Est. Priority Date: 03/22/2002
• Status: Expired due to Term

• Current Assignee: Gamehancement LLC (Jeffrey M. Gross)
• Original Assignee: Gula Consulting Limited Liability Company (Intellectual Ventures LLC)
• Inventors: Deering, Michael F., Lavelle, Michael G.
• Primary Examiner(s): Richer, Joni
• Application Number:
  US15/331,762
• Publication Number:
  US 20170103494A1
• Time in Patent Office: 627 Days
• Field of Search: None
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 5/70 Denoising; Smoothing

Abstract

A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Claims

1. An apparatus, comprising:

a memory, associated with a node of a ring topology, that stores one or more samples of an interleave of a super-sampled frame buffer, wherein the memory is dedicated to the interleave; and

a processor that, in response to receipt of a graphics primitive loop packet, executes a graphics rendering specified in the graphics primitive loop packet.

2. The apparatus of claim 1, wherein the processor is dedicated to the interleave.

3. The apparatus of claim 1, wherein the processor accesses a texture store in the memory in accordance with the graphics primitive loop packet.

4. The apparatus of claim 3, wherein the processor, in response to receipt of a video pixel loop packet, retrieves the one or more samples and modifies the video pixel loop packet in accordance with the one or more samples to yield a modified video pixel loop packet.

5. The apparatus of claim 4, wherein the processor updates the texture store in the memory in accordance with the modified video pixel loop packet.

6. The apparatus of claim 4, wherein the processor:

identifies a subset of the one or more samples within an active area of a defined antialiasing filter; and

applies the antialiasing filter to the subset of the one or more samples to yield a partial convolution result.

7. The apparatus of claim 6, wherein the processor:

generates one or more convolution coefficients associated with a center point of the antialiasing filter and the subset of the one or more samples;

performs a convolution of the subset of the one or more samples using the one or more convolution coefficients; and

performs a partial summation of a result of the convolution with one or more partial results contained in the video pixel loop packet.

8. The apparatus of claim 1, wherein the processor, in response to receiving a draw pixel loop packet, performs a conditional sample update function on the one or more samples of the interleave.

9. The apparatus of claim 1, further comprising a loop interface that exchanges one or more data packets with the ring topology.

10. The apparatus of claim 1, wherein the interleave is non-redundant with respect to interleaves of the super-sampled frame buffer assigned to other nodes on the ring topology.

11. A method, comprising:

storing, by a system comprising a processor, samples of an interleave of a super-sampled frame buffer in a memory associated with a node of a ring topology, wherein the node is dedicated to the interleave; and

in response to receiving a graphics primitive loop packet, executing a graphics rendering specified in the graphics primitive loop packet.

12. The method of claim 11, wherein the executing the graphics rendering comprises accessing a texture store in the memory in accordance with the graphics primitive loop packet.

13. The method of claim 12, further comprising, in response to receipt of a video pixel loop packet:

retrieving the samples, and

modifying the video pixel loop packet in accordance with the samples to yield a modified video pixel loop packet.

14. The method of claim 13, further comprising updating the texture store in the memory in accordance with the modified video pixel loop packet.

15. The method of claim 13, further comprising, in response to the receipt of the video pixel loop packet:

identifying a subset of the samples within an active area of a defined antialiasing filter; and

applying the antialiasing filter to the subset of the samples to yield a partial convolution result.

16. The method of claim 15, further comprising, in response to the receipt of the video pixel loop packet:

generating a convolution coefficient associated with a center point of the antialiasing filter and the subset of the samples;

performing convolution of the subset of the samples using the convolution coefficient; and

performing a partial summation of a result of the convolution with a partial result contained in the video pixel loop packet.

17. The method of claim 11, further comprising, in response to receiving a draw pixel loop packet, performing a conditional sample update function on the samples of the interleave.

18. A computer-readable storage device having stored thereon computer-executable instructions that, in response to execution, cause a computer system to perform operations, comprising:

maintaining at least one sample of an interleave of a super-sampled frame buffer in a memory of a node of a loop architecture, wherein the node is dedicated to the interleave; and

in response to receiving a graphics primitive loop packet, executing a graphics rendering specified in the graphics primitive loop packet.

19. The computer-readable storage device of claim 18, wherein the operations further comprise:

in response to receiving a draw pixel loop packet, performing a conditional sample update function on the at least one sample of the interleave.

20. The computer-readable storage device of claim 18, wherein the operations further comprise:

in response to receiving a video pixel loop packet;

retrieving the at least one sample of the interleave from the memory; and

modifying the video pixel loop packet in accordance with the at least one sample to yield a modified video pixel loop packet.