Location-based optimization for memory systems

• US 10,020,031 B2
• Filed: 01/09/2017
• Issued: 07/10/2018
• Est. Priority Date: 05/21/2015
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Chong, Yew Keong, Chen, Andy Wangkun, Thyagarajan, Sriram, Yeung, Gus, Dodrill, James Dennis
• Primary Examiner(s): Tran, Michael
• Application Number:
  US15/401,588
• Publication Number:
  US 20170117022A1
• Time in Patent Office: 547 Days
• Field of Search: 365154, 3652335, 36523008
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 29/702 by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

Claims

1. A method to fabricate a circuit for a memory having a set of memory blocks, the method comprising:

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, replacing mux instances in the first instantiation of the first memory block with faster mux instances to generate a second instantiation of the first memory block;

generating an instantiation of the memory based upon the second instantiation of the first memory block and the first instantiation of each memory block other than the first memory block; and

provided the instantiation of the memory fails timing specifications, testing time specifications for the first instantiation of a second memory block.

2. The method as set forth in claim 1, further comprising:

provided the first instantiation of the second memory block fails timing specifications for a signal path to the second memory block and a signal path from the second memory block, replacing mux instances in the first instantiation of the second memory block with faster mux instances to generate a second instantiation of the second memory block.

3. A method to fabricate a circuit for a memory having a set of memory blocks, the method comprising:

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, replacing mux instances in the first instantiation of the first memory block with faster mux instances to generate a second instantiation of the first memory block; and

provided the first instantiation of a first memory block fails timing specifications for a signal path from the first memory block but passes timing specifications for a signal path to the first memory block, generating a second instantiation of the first memory block with a faster bank instance than that of the first instantiation of the first memory block.

4. The method as set forth in claim 3, further comprising:

generating an instantiation of the memory based upon the second instantiation of the first memory block and the first instantiation of each memory block other than the first memory block;

provided the instantiation of the memory fails timing specifications, testing time specifications for the first instantiation of a second memory block; and

provided the first instantiation of the second memory block fails timing specifications for a signal path to the second memory block and a signal path from the second memory block, replacing mux instances in the first instantiation of the second memory block with faster mux instances to generate a second instantiation of the second memory block.

5. A method to fabricate a circuit for a memory having a set of memory blocks, the method comprising:

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, replacing mux instances in the first instantiation of the first memory block with faster mux instances to generate a second instantiation of the first memory block; and

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block but passes timing specifications for a signal path from the first memory block, generating a second instantiation of the first memory block with faster bit cell instances than that of the first instantiation of the first memory block.

6. The method as set forth in claim 5, further comprising:

generating an instantiation of the memory based upon the second instantiation of the first memory block and the first instantiation of each memory block other than the first memory block;

provided the instantiation of the memory fails timing specifications, testing time specifications for the first instantiation of a second memory block; and

provided the first instantiation of the second memory block fails timing specifications for a signal path to the second memory block and a signal path from the second memory block, replacing mux instances in the first instantiation of the second memory block with faster mux instances to generate a second instantiation of the second memory block.

7. A method to fabricate a circuit for a memory having a set of memory blocks, the method comprising:

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, replacing mux instances in the first instantiation of the first memory block with faster mux instances to generate a second instantiation of the first memory block;

generating one or more files for mask generation based at least in part on the instantiation of the memory; and

fabricating at least one mask based upon the one or more files.

8. A method to fabricate a circuit for a memory having a set of memory blocks, the method comprising:

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, generating a second instantiation of the first memory block with faster speed than that of the first instantiation of the first memory block;

generating an instantiation of the memory based upon the second instantiation of the first memory block and the first instantiation of each memory block other than the first memory block; and

provided the instantiation of the memory fails timing specifications, testing time specifications for the first instantiation of a second memory block.

9. The method as set forth in claim 8, further comprising:

provided the first instantiation of the second memory block fails timing specifications for a signal path to the second memory block and a signal path from the second memory block, generating a second instantiation of the second memory block with faster speed than that of the first instantiation of the second memory block.

12. A method as set forth in claim 8, further-to fabricate a circuit for a memory having a set of memory blocks, the method comprising:

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, generating a second instantiation of the first memory block with faster speed than that of the first instantiation of the first memory block; and

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block but passes timing specifications for a signal path from the first memory block, generating a second instantiation of the first memory block with a faster setup time than that of the first instantiation of the first memory block.

13. The method as set forth in claim 12, further comprising:

generating an instantiation of the memory based upon the second instantiation of the first memory block and the first instantiation of each memory block other than the first memory block;

provided the instantiation of the memory fails timing specifications, testing time specifications for the first instantiation of a second memory block; and

provided the first instantiation of the second memory block fails timing specifications for a signal path to the second memory block and a signal path from the second memory block, generating a second instantiation of the second memory block with faster speed than that of the first instantiation of the second memory block.

10. A method to fabricate a circuit for a memory having a set of memory blocks, the method comprising:

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, generating a second instantiation of the first memory block with faster speed than that of the first instantiation of the first memory block; and

provided the first instantiation of a first memory block fails timing specifications for a signal path from the first memory block but passes timing specifications for a signal path to the first memory block, generating a second instantiation of the first memory block with faster access time than that of the first instantiation of the first memory block.

11. The method as set forth in claim 10, further comprising:

generating an instantiation of the memory based upon the second instantiation of the first memory block and the first instantiation of each memory block other than the first memory block;

provided the instantiation of the memory fails timing specifications, testing time specifications for the first instantiation of a second memory block; and

provided the first instantiation of the second memory block fails timing specifications for a signal path to the second memory block and a signal path from the second memory block, generating a second instantiation of the second memory block with faster speed than that of the second instantiation of the first memory block.

14. A method to fabricate a circuit for a memory having a set of memory blocks, the method comprising:

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, generating a second instantiation of the first memory block with faster speed than that of the first instantiation of the first memory block; and

generating one or more files for mask generation based at least in part upon the instantiation of the memory; and

fabricating at least one mask based upon the one or more files.

15. An apparatus to fabricate a circuit for a memory having a set of memory blocks, comprising:

a memory to store instructions; and

a processor coupled to the memory that when executing the stored instructions performs a method comprising;

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, replacing mux instances in the first instantiation of the first memory block with faster mux instances to generate a second instantiation of the first memory block, or generating a second instantiation of the first memory block with faster speed than that of the first instantiation of the first memory block;

generating an instantiation of the memory based upon the second instantiation of the first memory block and the first instantiation of each memory block other than the first memory block; and

provided the instantiation of the memory fails timing specifications, testing time specifications for the first instantiation of a second memory block.

16. The apparatus as set forth in claim 15, the method further comprising:

provided the first instantiation of the second memory block fails timing specifications for a signal path to the second memory block and a signal path from the second memory block, replacing mux instances in the first instantiation of the second memory block with faster mux instances to generate a second instantiation of the second memory block or generating a second instantiation of the second memory block with faster speed than that of the first instantiation of the second memory block.

17. An apparatus to fabricate a circuit for a memory having a set of memory blocks, comprising:

a memory to store instructions; and

a processor coupled to the memory that when executing the stored instructions performs a method comprising;

generating a first instantiation for each memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block and a signal path from the first memory block, replacing mux instances in the first instantiation of the first memory block with faster mux instances to generate a second instantiation of the first memory block, or generating a second instantiation of the first memory block with faster speed than that of the first instantiation of the first memory block;

provided the first instantiation of a first memory block fails timing specifications for a signal path from the first memory block but passes timing specifications for a signal path to the first memory block, generating a second instantiation of the first memory block with a faster bank than that of the first instantiation of the first memory block or generating a second instantiation of the first memory block with faster access time than that of the first instantiation of the first memory block; and

provided the first instantiation of a first memory block fails timing specifications for a signal path to the first memory block but passes timing specifications for a signal path from the first memory block, generating a second instantiation of the first memory block with faster bit cell instances than that of the first instantiation of the first memory block or generating a second instantiation of the first memory block with a faster setup time than that of the first instantiation of the first memory block.