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Plated terminations

  • US 10,020,116 B2
  • Filed: 11/17/2016
  • Issued: 07/10/2018
  • Est. Priority Date: 04/15/2002
  • Status: Active Grant
First Claim
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1. A method of making a multi-layer electronic component, comprising the steps of:

  • providing a plurality of dielectric layers, each dielectric layer being delimited laterally by edges;

    interleaving a plurality of internal electrode elements among selected of said plurality of dielectric layers, such that selected portions of said plurality of internal electrode elements extend to and are exposed along at least one edge of said plurality of dielectric layers, said interleaved combination of electrode elements and dielectric layers forming a monolithic assembly characterized by respective opposing major surfaces thereof;

    providing a plurality of internal anchor tabs interleaved among selected of said plurality of dielectric layers and exposed along selected edges of said plurality of dielectric layers;

    configuring said plurality of internal electrode elements in a generally interdigitated configuration with multiple electrode tab portions extending from one or more selected sides of selected internal electrode elements such that the electrode tab portions are exposed at a predetermined number of multiple aligned columns at peripheral locations within a predetermined distance from each other of no more than about ten microns on the multi-layer electronic component;

    applying at least a pair of plated terminations over selected of said multiple aligned columns, respectively, of exposed electrode tab portions so that a predetermined distance is formed between such plated terminations; and

    wherein said monolithic assembly satisfies the structural relationship of T=about (¼

    ) W, where a dimension of the assembly measured in a direction interconnecting lateral surfaces is W and a dimension thereof measured in a direction interconnecting opposing major surfaces thereof is T.

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