Protrusion bump pads for bond-on-trace processing

• US 10,020,276 B2
• Filed: 11/08/2016
• Issued: 07/10/2018
• Est. Priority Date: 01/06/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chen-Shien, Chen, Yu-Feng, Lin, Yu-Wei, Kuo, Tin-Hao, Liang, Yu-Min, Lin, Chun-Hung
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US15/346,493
• Publication Number:
  US 20170053885A1
• Time in Patent Office: 609 Days
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector

Abstract

An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.

Claims

1. A method comprising:

forming an outermost dielectric layer;

forming a conductive trace in the outermost dielectric layer; and

forming a bump pad on the conductive trace, wherein the bump pad extends higher than a top surface of the outermost dielectric layer, wherein a surface of the bump pad opposite the conductive trace is substantially level, wherein the bump pad comprises a first lengthwise axis having a first dimension and a widthwise axis having a second dimension, wherein a ratio of the first dimension to the second dimension is about 0.8 to about 1.2, and wherein an outermost perimeter of the bump pad is disposed fully within an outermost perimeter of the conductive trace in a top-down view.

2. The method of claim 1 further comprising bonding a die to the conductive trace, wherein bonding the die comprises bonding a conductive bump of the die to the bump pad.

3. The method of claim 2, wherein bonding the die comprises disposing a second lengthwise axis of the conductive bump to be substantially parallel with the first lengthwise axis of the bump pad.

4. The method of claim 2, wherein bonding the die comprises disposing a second lengthwise axis of the conductive bump to intersect the first lengthwise axis of the bump pad.

5. The method of claim 2, wherein the conductive bump comprises a solder region, and wherein bonding the die comprises disposing the solder region in contact with a top surface and sidewalls of the bump pad.

6. The method of claim 2, wherein the conductive bump completely overlaps the bump pad in a top-down view.

7. The method of claim 1, wherein a top surface of the conductive trace comprises:

a first portion lower than the top surface of the outermost dielectric layer; and

a second portion forming an interface with the bump pad, wherein the second portion of the top surface of the conductive trace is higher than the first portion of the top surface of the conductive trace.

8. A method comprising:

exposing a surface of a conductive trace, wherein the conductive trace is at least partially disposed in a dielectric layer over a substrate;

disposing a conductive pad on the surface of the conductive trace, wherein the conductive pad comprises;

a lengthwise axis having a first dimension; and

a widthwise axis perpendicular to the lengthwise axis and having a second dimension, wherein a ratio of the first dimension to the second dimension is about 0.8 to about 1.2; and

recessing a first portion of the surface of the conductive trace not covered by the conductive pad, wherein after recessing the first portion of the surface of the conductive trace, the first portion of the surface of the conductive trace is lower than a second portion of the surface of the conductive trace covered by the conductive pad.

9. The method of claim 8, wherein the conductive pad is disposed on a conductive trace pad portion of the conductive trace, wherein the conductive trace pad portion has a third dimension measured along a second widthwise axis of the conductive trace pad portion, wherein the second widthwise axis of the conductive trace pad portion is parallel to and overlaps the widthwise axis of the conductive pad in a top-down view, wherein the third dimension is greater than a fourth dimension of the conductive trace taken along a third widthwise axis of the conductive trace parallel to the second widthwise axis of the conductive trace pad portion.

10. The method of claim 9, wherein the third dimension is less than the second dimension.

11. The method of claim 9, wherein the third dimension is greater than the second dimension.

12. The method of claim 9, wherein the third dimension is equal to the second dimension.

13. The method of claim 8 further comprising bonding a die to conductive trace, wherein bonding the die comprises directly bonding a solder region of the die to the conductive pad.

14. The method of claim 13, wherein bonding the die comprises disposing a lengthwise axis of the solder region substantially parallel with the lengthwise axis of the conductive pad.

15. The method of claim 13, wherein bonding the die comprises disposing a lengthwise axis of the solder region intersecting the lengthwise axis of the conductive pad in a top down view of the die.

16. A method comprising:

forming a dielectric layer over a substrate;

disposing a conductive trace at least partially in the dielectric layer;

forming a bump pad on the conductive trace, wherein the bump pad extends farther from the substrate than the dielectric layer, and wherein a ratio of a first length of the bump pad to a first width of the bump pad is about 0.8 to about 1.2, wherein the first length is taken along a first axis extending through a center of the bump pad, and wherein the first width is taken along a second axis perpendicular to the first axis and extending through the center of the bump pad; and

bonding a die to the conductive trace using a solder region, wherein the solder region is disposed over and along sidewalls of the bump pad, and wherein the solder region extends from a top surface of the bump pad to contact a top surface of the conductive trace.

17. The method of claim 16, wherein the solder region comprises a second length taken along a third axis extending through the center of the solder region, and wherein bonding the die comprises positioning the solder region so that the third axis is substantially parallel to the first axis in a top down view.

18. The method of claim 17, wherein bonding the die further comprises bonding an additional solder region to an additional bump pad, wherein the additional solder region comprises a third length taken along a fourth axis extending through the center of the additional solder region, and wherein bonding the die comprises positioning the additional solder region so that the third axis and the fourth axis are substantially parallel in a top down view.

19. The method of claim 17, wherein bonding the die further comprises bonding an additional solder region to an additional bump pad, wherein the additional solder region comprises a third length taken along a fourth axis extending through the center of the additional solder region, and wherein bonding the die comprises positioning the additional solder region so that the third axis and the fourth axis are not parallel in a top down view.

20. The method of claim 17, wherein the third axis is not parallel or perpendicular to an outer sidewall of the dielectric layer in a top down view.