Circuit substrate and method for manufacturing circuit substrate

• US 10,020,277 B2
• Filed: 01/31/2017
• Issued: 07/10/2018
• Est. Priority Date: 02/03/2016
• Status: Active Grant

• Current Assignee: Fujifilm Business Innovation Corp. (Fujifilm Holdings Corporation)
• Original Assignee: Fuji Xerox Company Limited (Fujifilm Holdings Corporation), Noda Screen Co., Ltd.
• Inventors: Iguchi, Daisuke, Hattori, Atsunori
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US15/421,018
• Publication Number:
  US 20170221848A1
• Time in Patent Office: 525 Days
• Field of Search: 257737
• CPC Class Codes: H01L 21/4875 Connection or disconnection of other leads to or from bases or plates
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/492 Bases or plates or solder therefor
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate

Abstract

A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.

Claims

1. A method for manufacturing a circuit substrate including a capacitor layer which includes a first metal layer, a dielectric layer which is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer, in which the first metal layer includes a first electrode region which is provided on a base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected, and the second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected, the method comprising:

forming the dielectric layer on a first base material;

forming the first metal layer on the dielectric layer;

placing the first base material, the formed dielectric layer, and the formed first metal layer on a second base material such that the first metal layer is positioned closer than the dielectric layer to the second base material;

removing all the first base material from the dielectric layer; and

forming the second metal layer on the dielectric layer after removing all the first base material from the dielectric layer.

2. The method for manufacturing a circuit substrate according to claim 1,

wherein the first base material is a metal.

3. The method for manufacturing a circuit substrate according to claim 1,

wherein a heat resistance temperature of the first base material is higher than a heat resistance temperature of the second base material.

4. The method for manufacturing a circuit substrate according to claim 1,

wherein removing the first base material includes removing the first base material with a solution.

5. The method for manufacturing a circuit substrate according to claim 1,

wherein the front surface of the second base material has flexibility at a time point when the dielectric layer which is formed on the first base material and the first metal layer are displaced on the second base material,

forming the first metal layer includes a step for patterning the first metal layer, and

moving the dielectric layer which is formed on the first base material and the first metal layer on the second base material, at least one portion of the patterned first metal layer is embedded on a front surface of the second base material.

6. The method for manufacturing a circuit substrate according to claim 1,

wherein forming the dielectric layer includes patterning the dielectric layer, and

forming the first metal layer includes forming the first metal layer on the dielectric layer and on the first base material on which the dielectric layer is not present.

7. The method for manufacturing a circuit substrate according to claim 6,

wherein forming the second metal layer includes

connecting the second metal layer and the first metal layer by forming the second metal layer so as to cover the dielectric layer and the first metal layer, and

separating the second metal layer into a metal layer which serves as the first electrode region, and a metal layer which serves as the second electrode region.

8. The method for manufacturing a circuit substrate according to claim 1,

wherein the first metal layer and the dielectric layer are formed on the second base material such that at least a part of the region of the first metal layer is exposed from the dielectric layer in a state where the dielectric layer and the first metal layer are displaced on the second base material, and

the second metal layer is formed on the dielectric layer such that the part of the region of the first metal layer is exposed from the dielectric layer.

9. The method for manufacturing a circuit substrate according to claim 1,

wherein the first base material is aluminum.

10. The method for manufacturing a circuit substrate according to claim 9, wherein the first metal layer and the second metal layer are copper.

11. A method for manufacturing a circuit substrate including a capacitor layer which includes a first metal layer, a dielectric layer which is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer, in which the first metal layer includes a first electrode region which is provided on a base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected, and the second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected, the method comprising:

forming the dielectric layer on a first base material;

forming the first metal layer on the dielectric layer;

placing the first base material, the formed dielectric layer and the formed first metal layer on a second base material such that the first metal layer is positioned closer than the dielectric layer to the second base material;

removing the first base material from the dielectric layer; and

forming the second metal layer on the dielectric layer after removing the first base material from the dielectric layer,

wherein the first base material is aluminum, and the first metal layer and the second metal layer are copper.

12. A method for manufacturing a circuit substrate including a capacitor layer which includes a first metal layer, a dielectric layer which is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer, in which the first metal layer includes a first electrode region which is provided on a base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected, and the second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected, the method comprising:

forming the dielectric layer on a first base material;

forming the first metal layer on the dielectric layer;

placing the formed dielectric layer and the formed first metal layer on a second base material such that the first metal layer is positioned closer than the dielectric layer to the second base material; and

forming the second metal layer on the dielectric layer which is placed on the second base material,

wherein the front surface of the second base material has flexibility at a time point when the dielectric layer which is formed on the first base material and the first metal layer are placed on the second base material, and

wherein the forming the first metal layer includes;

patterning the first metal layer, and

moving the formed dielectric layer and the first metal layer on the second base material, at least one portion of the patterned first metal layer is embedded on a front surface of the second base material.

13. A method for manufacturing a circuit substrate including a capacitor layer which includes a first metal layer, a dielectric layer which is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer, in which the first metal layer includes a first electrode region which is provided on a base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected, and the second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected, the method comprising:

forming the dielectric layer on a first base material;

forming the first metal layer on the dielectric layer;

placing the formed dielectric layer and the formed first metal layer on a second base material such that the first metal layer is positioned closer than the dielectric layer to the second base material; and

forming the second metal layer on the dielectric layer which is placed on the second base material,

wherein the forming the dielectric layer includes patterning the dielectric layer,

wherein the forming the first metal layer includes forming the first metal layer on the dielectric layer and on the first base material on which the dielectric layer is not present, and

wherein the forming the second metal layer includes;

connecting the second metal layer and the first metal layer by forming the second metal layer so as to cover the dielectric layer and the first metal layer, and

separating the second metal layer into a metal layer which serves as the first electrode region, and a metal layer which serves as the second electrode region.