Fin field effect transistor, semiconductor device and fabricating method thereof
First Claim
1. A method for fabricating a semiconductor device, comprising:
- patterning a substrate to form a plurality of trenches in the substrate and semiconductor fins between the trenches;
forming a plurality of insulators in the trenches;
forming a first dielectric layer to cover the semiconductor fins and the insulators;
forming at least one first dummy gate strip and at least one second dummy gate strip on the first dielectric layer, wherein lengthwise directions of the first and second dummy gate strips are different from a lengthwise direction of the semiconductor fins, and a width of the first dummy gate strip is smaller than a width of the second dummy gate strip;
forming a pair of first spacers and a pair of second spacers on sidewalls of the first and second dummy gate strips respectively;
removing the first dummy gate strip to form a first cavity;
removing the second dummy gate strip and the first dielectric layer underneath until sidewalls of the second spacers, a portion of the semiconductor fins and portions of the insulators are exposed to form a second cavity;
forming a second dielectric layer in the second cavity to selectively cover the exposed portion of the semiconductor fins, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer;
forming a first gate in the first cavity, wherein the first gate is in contact with the first dielectric layer; and
forming a second gate in the second cavity to cover the second dielectric layer, the exposed sidewalls of the spacers and the exposed portions of the insulators.
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Accused Products
Abstract
A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.
53 Citations
8 Claims
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1. A method for fabricating a semiconductor device, comprising:
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patterning a substrate to form a plurality of trenches in the substrate and semiconductor fins between the trenches; forming a plurality of insulators in the trenches; forming a first dielectric layer to cover the semiconductor fins and the insulators; forming at least one first dummy gate strip and at least one second dummy gate strip on the first dielectric layer, wherein lengthwise directions of the first and second dummy gate strips are different from a lengthwise direction of the semiconductor fins, and a width of the first dummy gate strip is smaller than a width of the second dummy gate strip; forming a pair of first spacers and a pair of second spacers on sidewalls of the first and second dummy gate strips respectively; removing the first dummy gate strip to form a first cavity; removing the second dummy gate strip and the first dielectric layer underneath until sidewalls of the second spacers, a portion of the semiconductor fins and portions of the insulators are exposed to form a second cavity; forming a second dielectric layer in the second cavity to selectively cover the exposed portion of the semiconductor fins, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer; forming a first gate in the first cavity, wherein the first gate is in contact with the first dielectric layer; and forming a second gate in the second cavity to cover the second dielectric layer, the exposed sidewalls of the spacers and the exposed portions of the insulators. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification