Dual channel trench LDMOS transistors with drain superjunction structure integrated therewith

• US 10,020,369 B2
• Filed: 02/01/2017
• Issued: 07/10/2018
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Mallikarjunaswamy, Shekar
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US15/422,340
• Publication Number:
  US 20170213894A1
• Time in Patent Office: 524 Days
• Field of Search: 257331, 257335, 257341-342
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7817 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7823 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7825 : with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain drift region of the first conductivity type formed in the semiconductor layer and in electrical contact with a drain electrode; and alternating N-type and P-type regions formed in the drain drift region with higher doping concentration than the drain-drift regions to form a super-junction structure in the drain drift region.

Claims

1. A semiconductor device comprising a dual channel trench LDMOS transistor, the dual channel trench LDMOS transistor comprising:

a semiconductor layer of a first conductivity type formed on a substrate;

a first trench formed in the semiconductor layer, the first trench being filled with a trench dielectric, a trench gate being formed in the first trench and insulated from the sidewall of the first trench by a first gate dielectric layer, the trench gate forming a vertical channel of the LDMOS transistor;

a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench;

a source region of the first conductivity type formed in the body region and adjacent the first trench;

a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region, the source region being formed aligned to a first edge of the planar gate, the planar gate forming a lateral channel of the LDMOS transistor;

a drain drift region of the first conductivity type formed in the semiconductor layer and in electrical contact with a drain electrode; and

a plurality of alternating N-type and P-type regions formed in the drain drift region, the plurality of alternating N-type and P-type regions having higher doping concentration than the drain-drift regions and forming a super-junction structure in the drain drift region.

2. The semiconductor device of claim 1, wherein the planar gate forms the lateral channel of the LDMOS transistor in the body region between the source region and the drain drift region, and the trench gate in the first trench forms the vertical channel of the LDMOS transistor in the body region along the sidewall of the first trench between the source region and the semiconductor layer.

3. The dual channel trench LDMOS transistor of claim 1, wherein the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity.

4. The dual channel trench LDMOS transistor of claim 3, wherein the plurality of alternating N-type and P-type regions comprises a first N-type region and a second N-type region and a P-type region sandwiched between the first and second N-type regions, the first and second N-type regions being self-aligned to a second edge of the planar gate and the P-type region being extended to the body region.

5. The dual channel trench LDMOS transistor of claim 3, wherein the plurality of alternating N-type and P-type regions comprises a first P-type region and a second P-type region and an N-type region sandwiched between the first and second P-type regions, the first and second P-type regions and the N-type region being self-aligned to a second edge of the planar gate.

6. The semiconductor device of claim 1, wherein the substrate comprises a substrate of the second conductivity type and the LDMOS transistor further comprises a drain region of the first conductivity type formed in the semiconductor layer, the drain region being spaced apart from the body region by the drain drift region, the drain region being electrically connected to the drain electrode.

7. The semiconductor device of claim 6, wherein the first trench extends through the semiconductor layer into the substrate, the trench gate being formed in an upper portion of the first trench and the semiconductor device further comprises:

a bottom gate electrode being formed in a lower portion of the first trench and insulated from the sidewall of the first trench by the trench dielectric having a second thickness, the second thickness being greater than the thickness of the first gate dielectric layer insulating the trench gate, the bottom gate electrode being electrically connected to a source potential.

8. The semiconductor device of claim 7, further comprising:

a second trench formed in the semiconductor layer and extending into the substrate, the second trench being filled with a trench dielectric, a trench gate being formed in an upper portion of the second trench and insulated from the sidewall of the second trench by a third gate dielectric layer, and a bottom gate electrode being formed in a lower portion of the second trench and insulated from the sidewall of the second trench by the trench dielectric, the trench dielectric having a thickness greater than the third gate dielectric layer, the trench gate being electrically floating or electrically connected to a given potential for deactivating the trench gate in the second trench, and the bottom gate electrode being electrically connected to a source potential,

wherein the second trench encircles active areas of the LDMOS transistor to provide electrical isolation of the LDMOS transistor.

9. The semiconductor device of claim 8, further comprising a MOS or bipolar transistor formed in the semiconductor layer adjacent to the second trench, the MOS or bipolar transistor being electrically isolated from the LDMOS transistor by the second trench.

10. The semiconductor device of claim 8, wherein the third gate dielectric layer has a thickness greater than the thickness of the first gate dielectric layer.

11. The semiconductor device of claim 6, wherein the first trench extends only into the semiconductor layer and the semiconductor device further comprises:

a second trench formed in the semiconductor layer and extending into the substrate, the second trench being filled with the trench dielectric,

wherein the second trench encircles active areas of the LDMOS transistor to provide electrical isolation of the LDMOS transistor.

12. The semiconductor device of claim 11, further comprising a MOS or bipolar transistor formed in the semiconductor layer adjacent to the second trench, the MOS or bipolar transistor being electrically isolated from the LDMOS transistor by the second trench.

13. The semiconductor device of claim 6, wherein the first trench extends through the semiconductor layer into the substrate, the trench gate being formed in an upper portion of the first trench, the semiconductor device further comprising:

a second trench formed in the semiconductor layer and extending into the substrate, the second trench being filled with the trench dielectric, a trench gate being formed in an upper portion of the second trench and insulated from the sidewall of the second trench by a third gate dielectric layer, the trench gate being electrically floating or electrically connected to a given potential for deactivating the trench gate in the second trench,

wherein the second trench encircles active areas of the LDMOS transistor to provide electrical isolation of the LDMOS transistor.

14. The semiconductor device of claim 13, wherein the third gate dielectric layer has a thickness greater than the thickness of the first gate dielectric layer.

15. The semiconductor device of claim 13, further comprising a MOS or bipolar transistor formed in the semiconductor layer adjacent to the second trench, the MOS or bipolar transistor being electrically isolated from the LDMOS transistor by the second trench.

16. The semiconductor device of claim 1, wherein the substrate comprises a substrate of the first conductivity type and the drain electrode comprises a backside drain electrode formed on a backside of the substrate, the dual channel trench LDMOS transistor forming a vertical trench LDMOS transistor.

17. The semiconductor device of claim 16, further comprising a vertical trench MOS transistor formed in a separate region of the same substrate and the same semiconductor layer, the vertical trench MOS transistor comprising:

a fourth trench formed in the semiconductor layer, the fourth trench being filled with a trench dielectric, a fourth trench gate being formed in the fourth trench and insulated from the sidewall of the fourth trench by a fourth gate dielectric layer;

a fourth body region of the second conductivity type formed in the semiconductor layer adjacent the fourth trench, the fourth body region extending to a depth near a bottom edge of the fourth trench gate formed in the fourth trench; and

a source region of the first conductivity type formed in the fourth body region and adjacent the fourth trench, the source region being formed in a top portion of the fourth body region,

wherein the vertical trench MOS transistor is formed with the substrate being a drain region, the semiconductor layer being a drain drift region, and the fourth trench gate being a gate electrode of the vertical trench MOS transistor.

18. The semiconductor device of claim 1, the trench gate and planar gate are electrically connected to a gate control signal to be turned on and off in unison.

19. The semiconductor device of claim 1, the trench gate is electrically connected to a trench gate control signal and the planar gate is electrically connected to a planar gate control signal so that the trench gate and the planar gate are to be turned on and off independently of each other.

20. The semiconductor device of claim 1, wherein the first trench extends through the semiconductor layer into the substrate, the trench gate being formed in an upper portion of the first trench.

21. The semiconductor device of claim 1, wherein the semiconductor layer comprises an epitaxial layer of the first conductivity type and the semiconductor layer further comprises a buried layer of the first conductivity type formed on the substrate, the epitaxial layer being formed on the buried layer.

22. The dual channel trench LDMOS transistor of claim 1, wherein the first conductivity type is P-type conductivity and the second conductivity type is PN-type conductivity.