Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors

• US 10,020,381 B1
• Filed: 05/17/2017
• Issued: 07/10/2018
• Est. Priority Date: 05/17/2017
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fan, Su Chen, Liu, Zuoguang, Wu, Heng, Yamashita, Tenko
• Primary Examiner(s): Fan, Bo
• Application Number:
  US15/597,662
• Time in Patent Office: 419 Days
• Field of Search: 257401, 438212, 438299
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.

Claims

1. A semiconductor device, comprising:

a semiconductor fin on a doped region of a substrate; and

an embedded bottom contact formed on a recessed portion of the doped region along three sides of the semiconductor fin;

wherein a conductivity of the embedded bottom contact is higher than a conductivity of the doped region.

2. The semiconductor device of claim 1, wherein the embedded bottom contact comprises a thickness of about 7 to about 12 nm.

4. The semiconductor device of claim 1, wherein the embedded bottom contact is recessed about 3 to about 5 nm below the bottom spacer.

3. A semiconductor device, comprising:

a semiconductor fin on a doped region of a substrate;

a conductive gate formed over a channel region of the semiconductor fin;

a bottom spacer between the conductive gate and the doped region;

a conductive rail on a recessed portion of the doped region;

a dielectric layer between the conductive rail and the conductive gate;

a first conductive contact on a surface of the conductive rail; and

a second conductive contact on a surface of the semiconductor fin;

wherein a conductivity of the conductive rail is higher than a conductivity of the doped region.