Integrated circuit devices and methods of manufacturing the same

• US 10,020,396 B2
• Filed: 11/14/2016
• Issued: 07/10/2018
• Est. Priority Date: 05/26/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cantoro, Mirco, Heo, Yeon-cheol, Toledano Luque, Maria
• Primary Examiner(s): Nicely, Joseph C
• Assistant Examiner(s): JEAN BAPTISTE, WILNER
• Application Number:
  US15/350,686
• Publication Number:
  US 20170345927A1
• Time in Patent Office: 603 Days
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.

Claims

1. An integrated circuit device comprising:

a substrate comprising a main surface;

a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and comprising a first section and a second section alternately arranged in the first direction, wherein the first section and the second section have the same composition as each other and have different crystal phases from each other;

a gate electrode covering the first section; and

a gate dielectric layer between the first section and the gate electrode.

2. The integrated circuit device of claim 1, wherein the substrate comprises a Group IV material or a Group III-V material, and

the main surface has a {11} crystal plane.

3. The integrated circuit device of claim 1, wherein the compound semiconductor nanowire comprises a Group III-V material.

4. The integrated circuit device of claim 1, wherein the compound semiconductor nanowire comprises at least one Group III element selected from indium (In), gallium (Ga), and aluminum (Al) and at least one Group V element selected from arsenic (As), phosphorus (P), and antimony (Sb), and

the first section and the second section have the different crystal phases respectively selected from a zinc-blende (ZB) crystal phase and a wurtzite (WZ) crystal phase.

5. The integrated circuit device of claim 1, wherein the compound semiconductor nanowire comprises two second sections that are in a pair respectively adjoining both ends of the first section with the first section in the middle,

wherein the first section has a first width in a second direction parallel to the main surface of the substrate, and

wherein the pair of second sections respectively have a second width in the second direction, wherein the second width is greater than the first width.

6. The integrated circuit device of claim 1, wherein the gate electrode has an annular shape surrounding the first section.

7. The integrated circuit device of claim 1, further comprising:

a source region in the substrate, the source region comprising a first dopant; and

a drain region in a portion of the compound semiconductor nanowire, the drain region comprising a second dopant,

wherein the first dopant and the second dopant comprise different elements from each other.

8. The integrated circuit device of claim 7, wherein the drain region is in the second section.

9. The integrated circuit device of claim 7, further comprising a conductive contact plug extending from the source region in the first direction so as to be parallel to the compound semiconductor nanowire.

10. The integrated circuit device of claim 1, further comprising a wiring layer contacting the gate electrode and extending parallel to the main surface of the substrate at a same level as that of the first section on the substrate.

11. An integrated circuit device comprising:

a substrate comprising a main surface;

a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and comprising a lower second section, a first section on the lower second section, and an upper second section on the first section,

wherein the first section has a different crystal phase from the upper second section and the lower second section;

a gate electrode on the first section,

wherein a portion of the gate electrode is between, in the first direction, the upper second section and the lower second section.

12. The integrated circuit device of claim 11, wherein the crystal phases of the first section, the upper second section, and the lower second section are selected from a zinc-blende (ZB) crystal phase and a wurtzite (WZ) crystal phase.

13. The integrated circuit device of claim 11, further comprising a gate dielectric layer between the first section and the gate electrode and covering sidewalls of the upper second section and the lower second section.

14. The integrated circuit device of claim 11, further comprising a wiring layer contacting the gate electrode and extending in a direction that is substantially parallel to the main surface of the substrate and substantially perpendicular to the first section.

15. The integrated circuit device of claim 11, wherein respective ends of the upper second section and the lower second section that are closest to the first section have a truncated shape having a decreasing width so as to have a decreasing cross-section area toward the first section.