Display substrate having improved manufacturability

• US 10,020,424 B2
• Filed: 03/07/2017
• Issued: 07/10/2018
• Est. Priority Date: 05/19/2016
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Park, Seung Hyun, Song, Jun Ho, Song, Jean Ho, Lee, Jae Hak
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US15/452,407
• Publication Number:
  US 20170336680A1
• Time in Patent Office: 490 Days
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H10K 50/805 Electrodes
• CPC Class Codes: H10K 50/813 characterised by their shape

Abstract

A display substrate is provided. The display substrate includes a gate electrode disposed on a base; a gate insulating layer disposed on the base and covering the gate electrode; a semiconductor layer disposed on the gate insulating layer and overlapping the gate electrode; a source electrode and a drain electrode disposed on the semiconductor layer and connected to the semiconductor layer; a pixel electrode disposed on the gate insulating layer, connected to the drain electrode, and extending from the drain electrode; a common electrode insulated from the pixel electrode and overlapping the pixel electrode; and a semiconductor pattern disposed between the gate insulating layer and the pixel electrode, the semiconductor pattern overlapping the pixel electrode. The semiconductor pattern comprises a same material as the semiconductor layer and extends from the semiconductor layer.

Claims

1. A display substrate, comprising:

a base;

a gate electrode disposed on the base;

a gate insulating layer disposed on the base and covering the gate electrode;

a semiconductor layer disposed on the gate insulating layer and overlapping the gate electrode;

a source electrode and a drain electrode disposed on the semiconductor layer and connected to the semiconductor layer;

a pixel electrode disposed on the gate insulating layer, connected to the drain electrode, and extending from the drain electrode;

a common electrode insulated from the pixel electrode and overlapping the pixel electrode; and

a semiconductor pattern disposed between the gate insulating layer and the pixel electrode, the semiconductor pattern overlapping the pixel electrode,

wherein the semiconductor pattern comprises a same material as the semiconductor layer and extends from the semiconductor layer.

2. The display substrate of claim 1, wherein a shape of the semiconductor pattern is substantially the same as a shape of the pixel electrode.

3. The display substrate of claim 1, wherein the pixel electrode comprises a same material as the drain electrode, and

wherein the pixel electrode does not contact an upper surface of the drain electrode.

4. The display substrate of claim 3, wherein:

the drain electrode includes a first sub-drain electrode which is disposed on the semiconductor layer, and a second sub-drain electrode which is disposed on the first sub-drain electrode; and

the pixel electrode includes a first sub-pixel electrode which is disposed on the gate insulating layer and which comprises a same material as the first sub-drain electrode, and a second sub-pixel electrode which is disposed on the first sub-pixel electrode and which comprises a same material as the second sub-drain electrode.

5. The display substrate of claim 4, wherein:

a shape of the first sub-drain electrode is substantially the same as a shape of the second sub-drain electrode; and

a shape of the first sub-pixel electrode is substantially the same as a shape of the second sub-pixel electrode.

6. The display substrate of claim 4, wherein:

the first sub-pixel electrode extends from the first sub-drain electrode; and

the second sub-pixel electrode extends from the second sub-drain electrode.

7. The display substrate of claim 4, wherein:

the drain electrode further includes a third sub-drain electrode, the third sub-drain electrode being disposed on the second sub-drain electrode and comprising a transparent conductive material; and

the pixel electrode further includes a third sub-pixel electrode, the third sub-pixel electrode being disposed on the second sub-pixel electrode and comprising a same material as the third sub-drain electrode.

8. The display substrate of claim 7, wherein:

a shape of the first sub-drain electrode, a shape of the second sub-drain electrode, and a shape of the third sub-drain electrode are substantially the same; and

a shape of the first sub-pixel electrode, a shape of the second sub-pixel electrode, and a shape of the third sub-pixel electrode are substantially the same.

9. The display substrate of claim 1, wherein:

at least one slit is formed in the pixel electrode; and

the common electrode has a planar shape, is disposed on the same layer as the gate electrode, and comprises a same material as the gate electrode.

10. The display substrate of claim 9, wherein the common electrode comprises a reflective metal.

11. The display substrate of claim 10, wherein:

the gate electrode includes a first sub-gate electrodes disposed on the base, and a second sub-gate electrode disposed on the first sub-gate electrode; and

the common electrode includes a first sub-common electrode disposed on the base and comprising a same material as the first sub-gate electrode, and a second sub-common electrode disposed on the first sub-common electrode and comprising a same material as the second sub-gate electrode.

12. The display substrate of claim 11, wherein:

a shape of the first sub-gate electrode is substantially the same as a shape of the second sub-gate electrode; and

a shape of the first sub-common electrode is substantially the same as a shape of the second sub-common electrode.

13. The display substrate of claim 11, wherein:

the gate electrode further includes a third sub-gate electrode disposed on the second sub-gate electrode; and

the common electrode further includes a third sub-common electrode disposed on the second sub-common electrode and comprising a same material as the third sub-gate electrode.

14. The display substrate of claim 9, further comprising:

an insulating layer disposed on the source electrode and the drain electrode, the insulating layer covering the semiconductor layer; and

a common voltage pad portion disposed on the same layer as the common electrode and electrically connected to the common electrode,

wherein a hole is formed in the gate insulating layer and the insulating layer so as to expose the common voltage pad portion.

15. The display substrate of claim 9, wherein the gate insulating layer has a portion having the same shape as the pixel electrode.

16. The display substrate of claim 1, further comprising:

an insulating layer disposed on the pixel electrode,

wherein;

the common electrode is disposed on the insulating layer and has one or more slits; and

the pixel electrode has a planar shape.

17. The display substrate of claim 16, wherein the pixel electrode comprises a reflective metal.

18. The display substrate of claim 16, further comprising:

a common voltage line disposed on the same layer as the gate electrode,

wherein;

a hole is formed in the gate insulating layer and the insulating layer so as to expose a portion of the common voltage line; and

the common electrode is electrically connected to the common voltage line through the hole.

19. A display substrate, comprising:

a base;

a semiconductor layer disposed on the base;

a gate insulating layer disposed on the base and covering the semiconductor layer;

a gate electrode disposed on the gate insulating layer and overlapping the semiconductor layer;

a common electrode disposed on the gate insulating layer and comprising a same material as the gate electrode;

an insulating layer disposed on the gate insulating layer and covering the gate electrode and the common electrode;

a source electrode and a drain electrode disposed on the insulating layer and connected to the semiconductor layer; and

a pixel electrode disposed on the insulating layer to overlap the common electrode, the pixel electrode being connected to the drain electrode so as to extend therefrom.

20. The display substrate of claim 19, wherein:

the common electrode has a planar shape; and

the pixel electrode has one or more slits.

21. The display substrate of claim 20, wherein the common electrode comprises a reflective metal.

22. The display substrate of claim 21, wherein:

the gate electrode includes a first sub-gate electrode disposed on the gate insulating layer, and a second sub-gate electrode disposed on the first sub-gate electrode; and

the common electrode includes a first sub-common electrode disposed on the gate insulating layer and comprising a same material as the first sub-gate electrode, and a second sub-common electrode disposed on the first sub-common electrode and comprising a same material as the second sub-gate electrode.

23. The display substrate of claim 22, wherein:

the gate electrode further includes a third sub-gate electrode disposed on the second sub-gate electrode and comprising a transparent conductive material; and

the common electrode further includes a third sub-common electrode disposed on the second sub-common electrode and comprising a same material as the third sub-gate electrode.

24. The display substrate of claim 19, wherein the pixel electrode comprises a same material as the drain electrode.

25. The display substrate of claim 24, wherein:

the drain electrode includes a first sub-drain electrode disposed on the insulating layer and connected to the semiconductor layer, and a second sub-drain electrode disposed on the first sub-drain electrode; and

the pixel electrode includes a first sub-pixel electrode disposed on the insulating layer and comprising a same material as the first sub-drain electrode, and a second sub-pixel electrode disposed on the first sub-pixel electrode and comprising a same material as the second sub-drain electrode.

26. The display substrate of claim 25, wherein:

a shape of the first sub-drain electrode is substantially the same as a shape of the second sub-drain electrode; and

a shape of the first sub-pixel electrode is substantially the same as a shape of the second sub-pixel electrode.

27. The display substrate of claim 25, wherein:

the first sub-pixel electrode extends from the first sub-drain electrode; and

the second sub-pixel electrode extends from the second sub-drain electrode.

28. The display substrate of claim 25, wherein:

the drain electrode further includes a third sub-drain electrode disposed on the second sub-drain electrode and comprising a transparent conductive material; and

the pixel electrode further includes a third sub-pixel electrode disposed on the second sub-pixel electrode and comprising a same material as the third sub-drain electrode.

29. The display substrate of claim 28, wherein:

a shape of the first sub-drain electrode, a shape of the second sub-drain electrode, and a shape of the third sub-drain electrode are substantially the same; and

a shape of the first sub-pixel electrode, a shape of the second sub-pixel electrode, and a shape of the third sub-pixel electrode are substantially the same.