Power loss protection integrated circuit with autonomous capacitor health check
First Claim
1. An integrated circuit comprising:
- an input voltage terminal (VIN);
an output voltage terminal (VOUT);
a current switch circuit that can receive a current of up to a maximum input current from the first terminal and can conduct that current to the output voltage terminal;
a storage capacitor terminal (STR);
a switch terminal (SW);
a feedback terminal (FB);
a buck/boost controller coupled to the switch terminal SW and to the feedback terminal FB, wherein the buck/boost controller is adapted to operate in a buck mode and in a boost mode, wherein in the buck mode the buck/boost controller drives the switch terminal SW so that the buck/boost controller in combination with an external inductor operates as a buck converter, wherein in the buck mode the buck converter receives a relatively high input supply voltage from the storage capacitor terminal STR, and wherein in the boost mode the buck/boost controller drives the switch terminal SW so that the buck/boost controller in combination with the external inductor operates as a boost converter and outputs a relatively high voltage onto the storage capacitor terminal STR;
a capacitor fault terminal (CF); and
an autonomous capacitor health check circuit adapted to sink a current from the storage capacitor terminal STR for a predetermined time duration, and during the predetermined time duration to detect whether a voltage on the storage capacitor terminal STR drops below a predetermined threshold voltage, and if the voltage on the storage capacitor terminal STR is detected to have dropped below the predetermined threshold voltage then the autonomous capacitor health check circuit asserts a digital logic signal onto the capacitor fault terminal CF, wherein the integrated circuit includes no processor that fetches, decodes and executes any instructions.
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Accused Products
Abstract
A power loss protection integrated circuit includes a storage capacitor terminal (STR), an autonomous capacitor health check circuit, and a capacitor fault terminal (CF). The capacitor health check circuit autonomously performs periodic capacitor check operations. In a check operation, current is sinked from the STR terminal for a predetermined time and in a predetermined way. If during this time the voltage on the STR terminal STR drops below a predetermined voltage, then a digital signal CF is asserted onto the CF terminal. Immediately following each capacitor check, a charging voltage is driven onto the STR terminal to recharge the external capacitors coupled to the STR terminal. In one example, the integrated circuit further includes a current switch circuit (eFuse) and a buck/boost controller. The capacitor health check circuit is only enabled during normal mode operation of the integrated circuit, and the check circuit disables boost operation during capacitor checks.
25 Citations
21 Claims
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1. An integrated circuit comprising:
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an input voltage terminal (VIN); an output voltage terminal (VOUT); a current switch circuit that can receive a current of up to a maximum input current from the first terminal and can conduct that current to the output voltage terminal; a storage capacitor terminal (STR); a switch terminal (SW); a feedback terminal (FB); a buck/boost controller coupled to the switch terminal SW and to the feedback terminal FB, wherein the buck/boost controller is adapted to operate in a buck mode and in a boost mode, wherein in the buck mode the buck/boost controller drives the switch terminal SW so that the buck/boost controller in combination with an external inductor operates as a buck converter, wherein in the buck mode the buck converter receives a relatively high input supply voltage from the storage capacitor terminal STR, and wherein in the boost mode the buck/boost controller drives the switch terminal SW so that the buck/boost controller in combination with the external inductor operates as a boost converter and outputs a relatively high voltage onto the storage capacitor terminal STR; a capacitor fault terminal (CF); and an autonomous capacitor health check circuit adapted to sink a current from the storage capacitor terminal STR for a predetermined time duration, and during the predetermined time duration to detect whether a voltage on the storage capacitor terminal STR drops below a predetermined threshold voltage, and if the voltage on the storage capacitor terminal STR is detected to have dropped below the predetermined threshold voltage then the autonomous capacitor health check circuit asserts a digital logic signal onto the capacitor fault terminal CF, wherein the integrated circuit includes no processor that fetches, decodes and executes any instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit, comprising:
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a first terminal; a second terminal; an eFuse circuit that can receive a current from the first terminal and can conduct the current to the second terminal in a non-fault condition, and that is adapted to decouple the first terminal from the second terminal in a fault condition such that in the fault condition there is no current flow between the first and second terminals; a third terminal; a fourth terminal for coupling to an external capacitor; and an autonomous capacitor health check circuit adapted to perform a capacitor health check operation, wherein a capacitor health check operation involves sinking a current from the fourth terminal for a predetermined time duration, and during the predetermined time duration detecting whether a voltage on the fourth terminal drops below a predetermined threshold voltage, and if the voltage on the fourth terminal is detected to have dropped below the predetermined threshold voltage then the autonomous capacitor health check circuit asserts a digital logic signal onto the third terminal, wherein the autonomous capacitor health check circuit periodically performs a capacitor health check operation without repeated prompting from any device outside the integrated circuit, and wherein the integrated circuit includes no processor that fetches, decodes and executes any instructions. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. An integrated circuit, comprising:
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an eFuse circuit; a boost controller; a terminal; and means for performing periodic autonomous capacitor health check operations on a capacitor coupled to the terminal, wherein a capacitor health check operation involves conducting a current from the terminal and detecting a voltage on the terminal, and wherein the integrated circuit includes no processor that fetches, decodes and executes any instructions. - View Dependent Claims (21)
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Specification