Error tolerant memory system

• US 10,020,822 B2
• Filed: 07/20/2015
• Issued: 07/10/2018
• Est. Priority Date: 07/21/2014
• Status: Active Grant

• Current Assignee: Rensselaer Polytechnic Institute
• Original Assignee: Rensselaer Polytechnic Institute
• Inventors: Zhang, Tong, Wang, Hao
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US15/323,598
• Publication Number:
  US 20170192691A1
• Time in Patent Office: 1,086 Days
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/154 Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial
• CPC Class Codes: H03M 13/1575 Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing

Abstract

A system and method of providing error tolerant memory access operations on a memory device. A method is disclosed including: providing location information of weak memory cells, wherein the location information includes addresses grouped into tiered sets, wherein each tiered set includes addresses having a number of weak memory cells; receiving a target address for a memory read operation; reading data from a virtual repair memory if the target address belongs to a first tiered set of addresses having a number of weak memory cells exceeding a threshold; and if the target address does not belong the first tiered set of addresses, reading data from the memory device and alternatively performing (a) an error correction and error detection (ECED) operation and (b) a target address look up operation, at different settings, until an error free result is obtained.

Claims

1. A system for handling memory access operations on a memory device, comprising:

a weak cell manager for storing location information of weak memory cells, wherein the location information includes addresses grouped into tiered sets based on a number of weak memory cells;

a virtual repair module that reads data from a virtual repair memory if a target address being read belongs to a first set of addresses having a number of weak memory cells exceeding a threshold;

an address check module that determines if the target address belongs to a selected set of addresses; and

a coding module that performs error and erasure correction when the address check module determines that the target address belongs to the selected set of addresses, and performs error correction and error detection when the address check module determines that the target address does not belong to the selected set of addresses.

2. The system of claim 1, wherein the coding module further performs error correction and error detection when the target address does not belong to the first set of addresses.

3. The system of claim 1, wherein the coding module is dynamically configurable to decode at different error detection, error correction and erasure correction settings.

4. The system of claim 1, wherein the memory device comprises a dynamic random access memory (DRAM).

5. The system of claim 1, wherein the address check module provides a location of each weak cell if the target address belongs to the selected set of target addresses.

6. The system of claim 1, wherein the virtual repair module writes data to the virtual repair memory during a write operation if the target address belongs to the first set of addresses.

7. The system of claim 6, wherein the virtual repair memory comprises a cache that includes a set of registers.