Vector signaling codes with high pin-efficiency for chip-to-chip communication and storage

• US 10,020,966 B2
• Filed: 12/23/2016
• Issued: 07/10/2018
• Est. Priority Date: 02/28/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin
• Primary Examiner(s): HA, DAC V
• Application Number:
  US15/390,293
• Publication Number:
  US 20170111192A1
• Time in Patent Office: 564 Days
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828

Abstract

An alternative type of vector signaling codes having increased pin-efficiency normal vector signaling codes is described. Receivers for these Permutation Modulation codes of Type II use comparators requiring at most one fixed reference voltage. The resulting systems can allow for a better immunity to ISI-noise than those using conventional multilevel signaling such as PAM-X. These codes are also particularly advantageous for storage and recovery of information in memory, as in a DRAM.

Claims

1. An apparatus comprising:

a plurality of groups of adjacent memory cells, each group of adjacent memory cells holding elements of a balanced, reference-less vector signaling codeword as charge levels;

a set of sense amplifiers connected to the plurality of groups of adjacent memory cells, each sense amplifier configured to receive at least two elements of the balanced, reference-less vector signaling codeword, the respective set of sense amplifiers configured to generate a plurality of sense amplifier values; and

a logic decoder configured to receive the plurality of sense amplifier values from the respective set of sense amplifiers and to responsively generate a set of output bits.

2. The apparatus of claim 1, wherein the balanced, reference-less vector signaling codeword comprises N elements and wherein the set of sense amplifiers comprises N comparators, wherein N is an integer greater than 1.

3. The apparatus of claim 1, wherein the set of sense amplifiers comprises at least

one sense amplifier configured to generate a sense amplifier value of the plurality of sense amplifier values by comparing an average of a first two elements of the balanced, reference-less vector signaling codeword to an average of a second two elements of the balanced, reference-less vector signaling codeword.

4. The apparatus of claim 3, further comprising parallel resistor networks configured to generate the averages of the first and second two elements of the balanced, reference-less vector signaling codeword.

5. The apparatus of claim 1, wherein the plurality of sense amplifiers comprises one or more multi-input comparators.

6. The apparatus of claim 5, wherein at least one of the multi-input comparators has two or more input weighting coefficients.

7. The apparatus of claim 5, wherein the one or more multi-input comparators have input weighting coefficients selected according to an orthogonal matrix.

8. The apparatus of claim 7, wherein the orthogonal matrix is a Hadamard matrix.

9. The apparatus of claim 1, further comprising:

an encoder configured to receive a set of information bits, and to responsively generate elements of a second balanced, reference-less vector signaling codeword; and

a memory write circuit configured to store the elements of the second balanced, reference-less vector signaling codeword in a selected group of adjacent memory cells.

10. The apparatus of claim 1, wherein the balanced, reference-less vector signaling codeword is a permutation modulation codeword.

11. A method comprising:

obtaining elements of a balanced, reference-less vector signaling codeword from a selected group of adjacent memory cells of a plurality of groups of adjacent memory cells, the selected group of adjacent memory cells holding the elements of the balanced, reference-less vector signaling codeword as charge levels;

generating, for the selected group of adjacent memory cells, a plurality of sense amplifier values using a set of sense amplifiers, each sense amplifier configured to receive at least two elements of the balanced, reference-less vector signaling codeword; and

generating a set of output bits by decoding the plurality of sense amplifier values.

12. The method of claim 11, wherein the balanced, reference-less vector signaling codeword comprises N elements, and wherein the set of sense amplifiers comprises N comparators, wherein N is an integer greater than 1.

13. The method of claim 11, wherein

generating at least one sense amplifier value of the plurality of sense amplifier values comprises comparing an average of a first two elements of the balanced, reference-less vector signaling codeword to an average of a second two elements of the balanced, reference-less vector signaling codeword.

14. The method of claim 13, wherein the averages of the first and second two elements of the balanced, reference-less vector signaling codeword are generated using parallel resistor networks.

15. The method of claim 11, wherein the plurality of sense amplifiers comprises one or more multi-input comparators.

16. The method of claim 15, wherein at least one of the multi-input comparators has two or more input weighting coefficients.

17. The method of claim 15, wherein the one or more multi-input comparators have input weighting coefficients selected according to an orthogonal matrix.

18. The method of claim 17, wherein the orthogonal matrix is a Hadamard matrix.

19. The method of claim 11, further comprising:

receiving a set of information bits;

generating elements of a second balanced, reference-less vector signaling codeword; and

storing the elements of the second balanced, reference-less vector signaling codeword in a selected group of adjacent memory cells.

20. The method of claim 11, wherein the balanced, reference-less vector signaling codeword is a permutation modulation codeword.