Display device with capping layer

• US 10,025,130 B2
• Filed: 12/18/2015
• Issued: 07/17/2018
• Est. Priority Date: 12/18/2015
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Jongbin, Kim, YoungJoo, Kim, Donghyun
• Primary Examiner(s): Rabindranath, Roy P
• Application Number:
  US14/975,611
• Publication Number:
  US 20170176797A1
• Time in Patent Office: 942 Days
• Field of Search: 345173-178
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G06F 2203/04111 Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Abstract

A display of an electric device includes a plurality of separated transparent electrode blocks, which are configured to provide one or more of supplemental features such as touch recognition. Signal paths between the transparent electrode blocks and the driver for the supplemental feature are implemented with a plurality of conductive lines placed under positioned under one or more planarization layers. The conductive lines implementing the signal paths are routed across the display area, directly toward a non-display area where drive-integrated circuits are located.

Claims

1. A liquid crystal display device with a touch sensor, comprising:

a plurality of pixels, each pixel including a thin-film transistor (TFT) and a pixel electrode, the TFT interposed between a lower planarization layer and an upper planarization layer, and the pixel electrode provided on the upper planarization layer;

a touch driver;

a plurality of common signal lines under the lower planarization layer, the plurality of common signal lines connected to the touch driver;

a plurality of bypass lines provided between the lower planarization layer and the upper planarization layer, each of the bypass lines in direct contact with at least one of the common signal lines via a contact hole through the lower planarization layer;

one or more passivation layers provided under the upper planarization layer; and

a common electrode layer on the upper planarization layer, the common electrode layer including separated pieces of common electrode blocks, each of the common electrode blocks connected to at least one of the bypass lines via a contact hole through the upper planarization layer,

wherein said one or more passivation layers under the upper planarization layer include a passivation layer formed on an upper surface of the lower planarization layer.

2. The liquid crystal display device with the touch sensor of claim 1, wherein the lower planarization layer includes an organosiloxane hybrid layer including Si—

O monomer and polymer.

3. The liquid crystal display device with the touch sensor of claim 2, wherein the lower planarization layer includes a hybrid polysiloxane polymer layer containing organic contents including alkyl and aryl functionalities.

4. The liquid crystal display device with the touch sensor of claim 2, wherein the common signal lines are formed of a stack of multiple metal layers including a copper layer.

5. The liquid crystal display device with the touch sensor of claim 3, wherein said one or more passivation layers under the upper planarization layer include a passivation layer formed on a lower surface of the lower planarization layer.

6. The liquid crystal display device with the touch sensor of claim 5, wherein the passivation layer formed on the lower surface of the lower planarization layer includes a silicon nitride layer.

7. The liquid crystal display device with the touch sensor of claim 1, wherein the lower planarization layer includes a hybrid polysiloxane polymer layer expressed in a chemical formula 1.

8. The liquid crystal display device with the touch sensor of claim 1, wherein the passivation layer formed on the upper surface of the lower planarization layer includes a silicon nitride layer.

9. The liquid crystal display device with the touch sensor of claim 8, wherein the TFT has a staggered structure type TFT.

10. The liquid crystal display device with the touch sensor of claim 8, wherein the TFT is a coplanar structure type TFT.

11. The liquid crystal display device with the touch sensor of claim 1, comprising a first passivation layer formed on a lower surface of the lower planarization layer and a second passivation layer formed on an upper surface of the lower planarization layer, wherein the first passivation layer includes a silicon nitride layer.

12. The liquid crystal display device with the touch sensor of claim 1, wherein the TFT has a metal oxide semiconductor.

13. An electronic device with a display, comprising:

a display area provided with a plurality of pixels;

a non-display area provided with a driver;

a layer of thin-film-transistor (TFT) array arranged in the display area;

a plurality of separated transparent electrode blocks provided above the layer of TFT array and arranged to overlap with the plurality of pixels in the display area;

a plurality of common signal lines provide under the layer of TFT array and configured to form a plurality of signal paths, each of the signal paths connecting each one of the plurality of separated transparent electrode block to the driver;

a passivation layer provided on the plurality of common signal lines;

a lower planarization layer provided on the passivation layer and below the layer of TFT array, wherein the lower planarization layer includes a hybrid poly-siloxane polymer layer; and

an upper planarization layer provided over the layer of TFT array and below the plurality of separated transparent electrode blocks,

wherein the layer of TFT array is disposed between the lower planarization layer and the upper planarization layer.

14. The electronic device with the display of claim 13, wherein the hybrid-siloxane polymer layer exhibits a thermal gravimetric analysis (TGA) rate of 1 percent or less at a temperature of 350 degrees Celsius for at least 30 minutes.

15. The electronic device with the display of claim 13, wherein the passivation layer provided on the plurality of common signal lines and under the lower planarization layer includes a silicon nitride layer.

16. The electronic device with the display of claim 15, further comprises another passivation layer on an upper surface of the lower planarization layer.

17. The electronic device with the display of claim 13, wherein the layer of TFT array includes a plurality of oxide metal semiconductor TFTs.

18. The electronic device with the display of claim 13, wherein the layer of TFT array includes a plurality of poly-silicon semiconductor TFTs.

19. The electronic device with the display of claim 13, wherein the layer of TFT array includes at least one oxide metal semiconductor TFT and at least one poly-silicon semiconductor TFT.