Adaptive timing configuration for athletic devices

• US 10,025,274 B2
• Filed: 10/13/2014
• Issued: 07/17/2018
• Est. Priority Date: 10/14/2013
• Status: Active Grant

• Current Assignee: Nike, Inc.
• Original Assignee: Nike, Inc.
• Inventors: Henderson, Kristofer, Bielman, James
• Primary Examiner(s): MULLEN, THOMAS J
• Application Number:
  US14/512,854
• Publication Number:
  US 20150103633A1
• Time in Patent Office: 1,373 Days
• Field of Search: 34030916, 368 10- 12
• CPC Class Codes: G04G 13/02 at preselected times, e.g. alarm clocks
• CPC Class Codes: G04G 19/12 Arrangements for reducing power consumption during storage
• CPC Class Codes: G04G 21/02 Detectors of external physical values, e.g. temperature
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality

Abstract

A system configured to allow one or more timing processes to accurately keep track of one or more timers while a processor executing the one or more timing processes is in a low-power operational mode. The system is configured to set a real-time clock alarm expiration time equal to a closest expiration time, from a current time, of the one or more timers. Accordingly, upon expiration of the real-time clock alarm, an interrupt is communicated to the processor, resulting in the processor being brought out of a low-power operational mode, and executing one or more processes associated with the corresponding expired timer.

Claims

1. An apparatus, comprising:

a sensor configured to output motion data indicative of an amount of acceleration of the apparatus;

a processor;

a real-time clock module implemented as an application-specific integrated circuit hardware element separate from the processor, comprising;

a real-time clock alarm module, operatively connected to the processor, and configured to trigger a real-time clock alarm at an alarm expiration time causing the real-time clock alarm to communicate an interrupt signal to the processor; and

a real-time clock calendar module, operatively connected to the real-time clock alarm module, and configured to communicate a real-time clock calendar time to the real-time clock alarm module, wherein the real-time clock alarm is triggered upon agreement of the alarm expiration time and the real-time clock calendar time;

memory storing computer-readable instructions that, when executed by the processor, cause the apparatus to;

store one or more timers in a queue, wherein each of the one or more timers comprises a value corresponding to a length of time from a current time, said current time indicated by the real-time clock calendar time, wherein said queue is ordered in order of increasing value of said one or more timers, and wherein a time between said one or more timers has any value;

identify, upon triggering of the real-time clock alarm, one or more expired timers from said one or more timers stored in the queue;

execute one or more processes associated with the one or more expired timers;

remove the one or more expired timers from the queue;

set, upon triggering of the real-time clock alarm, a new alarm expiration time equal to a time value that is an amount of time ahead of the real-time clock calendar time equal to a value of a first timer remaining in the queue; and

store a timeout timer in the queue if the motion data received from the sensor during a predetermined timeout time period indicates that the apparatus is not accelerating.

2. The apparatus of claim 1, wherein the computer-readable instructions, when executed by the processor, further cause the apparatus to:

set an operational mode of the processor upon setting the alarm expiration time.

3. The apparatus of claim 2, wherein the operational mode of the processor is a low-power operational mode.

4. The apparatus of claim 3, wherein the low-power operational mode operates the processor at a low frequency.

5. The apparatus of claim 1, wherein the interrupt signal wakes the processor from a low-power operational mode.

6. The apparatus of claim 5, wherein the low-power operational mode reduces power consumption by the processor by at least 90%.

7. A unitary apparatus configured to be worn by a user, comprising:

a structure configured to be worn around an appendage of a user, comprising;

a power supply;

a sensor configured to capture acceleration data from the appendage of the user;

a processor, operatively connected to the sensor, and configured to receive captured acceleration data;

a real-time clock alarm module, implemented as an application-specific integrated circuit hardware element separate from and operatively connected to the processor, and configured to trigger a real-time clock alarm causing the real-time clock alarm to communicate an interrupt signal to the processor upon agreement of an alarm expiration time and a current time;

a non-transitory computer-readable medium comprising computer-executable instructions that when executed by the processor cause the processor to perform at least the following;

store one or more timers in a data structure;

identify, upon triggering of the real-time clock alarm, one or more expired timers from the one or more timers stored in the data structure;

execute one or more processes associated with the one or more expired timers;

remove the one or more expired timers from the data structure;

set, upon triggering of the real-time clock alarm, a new alarm expiration time equal to a time value that is an amount of time ahead of the current time equal to a lowest value of the one or more timers in the data structure; and

store a timeout timer in the data structure if the acceleration data received during a predetermined timeout time period indicates that the unitary apparatus is not accelerating.

8. The unitary apparatus of claim 7, wherein the computer-executable instructions, when executed by the processor, further cause the processor to:

set an operational mode of the processor upon setting the alarm expiration time.

9. The unitary apparatus of claim 8, wherein the operational mode of the processor is a low-power operational mode.

10. The unitary apparatus of claim 9, wherein the low-power operational mode reduces power consumption by the processor by at least 90%.

11. The unitary apparatus of claim 9, wherein the computer-executable instructions, when executed by the processor, cause the processor to:

waken the processor from the low-power operational mode upon receipt of acceleration data with a predetermined acceleration characteristic.

12. The unitary apparatus of claim 7, wherein the interrupt signal wakes the processor from a low-power operational mode.

13. A non-transitory computer-readable medium comprising computer-executable instructions that when executed by a processor are configured to perform at least the following:

store one or more timers in a data structure;

identify, upon triggering of a real-time clock alarm associated with a real-time clock alarm module implemented as an application-specific integrated circuit hardware element separate from the processor, one or more timers, from the data structure, that will expire within a predetermined active time period from a current time indicated by a real-time clock calendar module;

execute one or more processes associated with the one or more timers that will expire during the predetermined active time period;

set a new alarm expiration time of the real-time clock alarm module equal to a future expiration time associated with a timer in the data structure, wherein the future expiration time is a closest expiration time, from the one or more timers, to the current time;

set a low-power operational mode of the processor upon setting the alarm expiration time; and

store a timeout timer in the data structure if no motion data is received by the real-time clock alarm module.

14. The non-transitory computer-readable medium of claim 13, wherein the real-time clock alarm module is configured to trigger an interrupt on the processor by outputting an interrupt signal that initiates a high-power operational mode of the processor, upon agreement of the alarm expiration time and the current time.

15. The non-transitory computer-readable medium of claim 13, wherein the low-power operational mode reduces a clock frequency of operation of the processor by at least 90%.