Memory system for portable telephone

• US 10,025,596 B2
• Filed: 09/16/2016
• Issued: 07/17/2018
• Est. Priority Date: 07/09/1999
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shinohara, Takayuki, Kimura, Masatoshi
• Primary Examiner(s): LEMMA, SAMSON B
• Application Number:
  US15/267,895
• Publication Number:
  US 20170003978A1
• Time in Patent Office: 669 Days
• Field of Search: 713193
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 16/13 File access structures, e.g. distributed indices arrangements of input from, or output to, record carriers G06F3/06
• CPC Class Codes: G06F 2207/7228 Random curve mapping, e.g. mapping to an isomorphous or projective curve
• CPC Class Codes: G06F 2213/3806 Mobile device
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 7/725 over elliptic curves
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: H04L 2209/08 Randomization, e.g. dummy operations or using noise
• CPC Class Codes: H04L 2209/56 Financial cryptography, e.g. electronic payment or e-cash
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/3066 involving algebraic varieties, e.g. elliptic or hyper-elliptic curves
• CPC Class Codes: H04M 1/026 Details of the structure or mounting of specific components
• CPC Class Codes: H04M 1/6505 storing speech in digital form
• CPC Class Codes: H04M 1/72403 with means for local support of applications that increase the functionality
• CPC Class Codes: H04M 2201/36 Memories
• CPC Class Codes: H04M 2250/14 including a card reading device

Abstract

A memory system is constituted of a file storage flash memory storing a control program required for a control portion and a large amount of data, and a random access memory storing a program used by the control portion and functioning as a buffer memory for received data. Thus, a memory system for a portable telephone capable of storing a large amount of received data at high-speed and allowing reading of the stored data at high-speed is provided.

Claims

1. A microprocessor chip comprising:

an MPU core;

a file storage flash memory;

a first bus configured to perform with a first command manner;

a second bus configured to perform with a second command manner different from the first command manner;

a bus converting circuit configured to interface between the first bus and the second bus; and

a random access memory,

wherein the first bus is coupled with the MPU core, the random access memory and the bus converting circuit, and

wherein the second bus is coupled with the file storage flash memory and the bus converting circuit.

2. The microprocessor chip according to claim 1,

wherein the MPU core includes a read only memory that is configured to store a routine for performing an initializing operation at power-on.

3. A microprocessor chip comprising:

a CPU;

a first memory and a second memory;

a first bus configured to perform with a first command manner;

a second bus configured to perform with a second command manner different from the first command manner; and

a bus converting circuit configured to interface between the first bus and the second bus,

wherein the first bus is coupled with the CPU, the first memory and the bus converting circuit, and

wherein the second bus is coupled with the second memory and the bus converting circuit.

4. The microprocessor chip according to claim 3,

wherein the CPU includes a read only memory that is configured to store a routine for performing an initializing operation at power-on.

5. The microprocessor chip according to claim 3,

wherein the first memory comprises a volatile memory, and

wherein the second memory comprises a non-volatile memory.

6. The microprocessor chip according to claim 5,

wherein the second memory is configured as a file storage.