Event rate change based hardware performance data collection

• US 10,025,687 B2
• Filed: 05/25/2016
• Issued: 07/17/2018
• Est. Priority Date: 05/25/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bangalore, Srinivas P., Nair, Sooraj R.
• Primary Examiner(s): Mehrmanesh, Elmira
• Application Number:
  US15/163,860
• Publication Number:
  US 20170344455A1
• Time in Patent Office: 783 Days
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 11/3495 for systems
• CPC Class Codes: G06F 2201/88 Monitoring involving counting

Abstract

An approach for writing performance data to memory based on a hardware event rate change involving receiving a hardware event count associated with a computer processor, comparing the hardware event count to a previous hardware event count, computing the hardware event rate change associated with a change between the hardware event count and the previous hardware event count and, responsive to the hardware event rate change not equaling a threshold rate, writing the hardware event count to memory.

Claims

1. A method for writing performance data to memory based on a hardware event rate change, the method comprising:

receiving a hardware event count associated with a computer processor;

creating a reference table comprising a plurality of nearest powers of two, wherein each nearest power of two corresponds to an associated most significant bit of a binary number;

retrieving a nearest power of two associated with the previous hardware event count;

comparing the hardware event count to a previous hardware event count;

computing the hardware event rate change associated with a change between the hardware event count and the previous hardware event count; and

responsive to the hardware event rate change not equaling a threshold rate, writing the hardware event count to memory.

2. The method of claim 1, wherein computing the hardware event rate change comprises computing a difference associated with subtracting the nearest power of two, associated with the previous hardware event count, from the hardware event count and right shifting the difference by the nearest power of two.

3. The method of claim 1, wherein computations associated with computing the hardware event rate change use a plurality of variables comprising rate, thresh, old_count, new_count and num_count.

4. The method of claim 3, wherein rate is associated with the hardware event rate change, thresh is associated with the threshold rate, old_count is associated with the previous hardware event count, new_count is associated with the hardware event count and num_count is associated with a number of times that a same value is received as the hardware event count.

5. The method of claim 4, wherein responsive to a determination that rate is not equal to thresh, new_count is written to memory.

6. The method of claim 1, wherein responsive to the hardware event rate change not equaling the threshold rate, the threshold rate is set as the hardware event rate change.

7. A computer system for writing performance data to memory based on a hardware event rate change, the computer system comprising:

one or more computer processors;

one or more computer readable storage media;

an event rate analyzer comprising a count comparator, a data writer, a rate calculator and a table creator;

program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising;

program instructions to receive a hardware event count associated with a computer processor;

program instructions to create a reference table comprising a plurality of nearest powers of two, wherein each nearest power of two corresponds to an associated most significant bit of a binary number;

program instruction to retrieve a nearest power of two associated with the previous hardware event count;

program instructions to compare the hardware event count to a previous hardware event count;

program instructions to compute the hardware event rate change associated with a change between the hardware event count and the previous hardware event count; and

program instructions to, responsive to the hardware event rate change not equaling a threshold rate, write the hardware event count to memory.

8. The computer system of claim 7, wherein the program instructions to compute the hardware event rate change comprise computing a difference associated with subtracting the nearest power of two, associated with the previous hardware event count, from the hardware event count and right shifting the difference by the nearest power of two.

9. The computer system of claim 7, wherein computations associated with the program instructions to compute the hardware event rate change use a plurality of variables comprising rate, thresh, old_count, new_count and num_count.

10. The computer system of claim 9, wherein rate is associated with the hardware event rate change, thresh is associated with the threshold rate, old_count is associated with the previous hardware event count, new_count is associated with the hardware event count and num_count is associated with a number of times that a same value is received as the hardware event count.

11. The computer system of claim 10, wherein responsive to a determination that rate is not equal to thresh, new_count is written to memory.

12. The computer system of claim 7, wherein responsive to the hardware event rate change not equaling the threshold rate, the threshold rate is set as the hardware event rate change.

13. An apparatus for writing performance data to memory based on a hardware event rate change, the apparatus comprising:

a count comparator for receiving a hardware event count associated with a computer processor and comparing the hardware event count to a previous hardware event count;

a table creator for creating a reference table comprising a plurality of nearest powers of two, wherein each nearest power of two corresponds to an associated most significant bit of a binary number and the count comparator retrieves a nearest power of two associated with the previous hardware event count;

a rate calculator for computing the hardware event rate change associated with a change between the hardware event count and the previous hardware event count; and

a data writer for writing the hardware event count to memory when the hardware event rate change does not equal a threshold rate.

14. The apparatus of claim 13, wherein the rate calculator computes a difference associated with subtracting the nearest power of two, associated with the previous hardware event count, from the hardware event count and right shifts the difference by the nearest power of two.

15. The apparatus of claim 13, wherein the rate calculator uses a plurality of variables comprising rate, thresh, old_count, new_count and num_count for computing the hardware event rate change.

16. The apparatus of claim 15, wherein rate is associated with the hardware event rate change, thresh is associated with the threshold rate, old_count is associated with the previous hardware event count, new_count is associated with the hardware event count and num_count is associated with a number of times that a same value is received as the hardware event count.

17. The apparatus of claim 13, wherein the rate calculator sets the threshold rate as the hardware event rate change when the hardware event rate change does not equal the threshold rate.