Exchange message protocol message transmission between two devices

• US 10,025,736 B1
• Filed: 04/17/2015
• Issued: 07/17/2018
• Est. Priority Date: 04/17/2014
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Ricaborda, Amor Leo Saing, Abitria, Alain Vincent Villaranda, Orcullo, Rose Fay M.
• Primary Examiner(s): Unelus, Ernest
• Application Number:
  US14/690,371
• Time in Patent Office: 1,187 Days
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

Abstract

In an embodiment of the invention, a method comprises: transmitting, by a host side, an exchange message protocol (EMP) command frame to a memory device side; informing, by the host side, the memory device side to process the command frame; executing, by the memory device side, the command frame; and transmitting, by the memory device side, an EMP response frame to the host side, in response to the command frame. In another embodiment of the invention, an apparatus comprises: a host side configured to transmit an exchange message protocol (EMP) command frame to a memory device side; wherein the host side is configured to inform the memory device side to process the command frame; wherein the memory device side is configured to execute the command frame; and wherein the memory device side is configured to transmit an EMP response frame to the host side, in response to the command frame.

Claims

1. A method, comprising:

transmitting, by a host side, an exchange message protocol (EMP) command frame to a memory device side;

wherein said transmitting further comprises posting, by the host side, the EMP command frame into a first memory array in the memory device side, wherein the host side is coupled by a bus to the memory device side;

wherein the memory device side comprises a non-volatile memory device;

informing, by the host side, the memory device side to process the command frame;

executing, by the memory device side, the command frame in response to the EMP command frame being posted into the first memory array;

posting, by the memory device side, an EMP response frame into a second memory array in the memory device side in response to the EMP command frame being executed by the memory device side;

transmitting, by the memory device side, the EMP response frame to the host side, in response to the EMP response frame being posted into the second memory array;

wherein the non-volatile memory device in the memory device side comprises a command ring comprising the first memory array and a response ring comprising the second memory array, and wherein the rings implement asynchronous communication between the host side and the memory device side and allow processing of multiple outstanding command frames and of multiple outstanding response frames;

wherein the command ring in the non-volatile memory device comprises a command get pointer and a command put pointer;

wherein the response ring comprises a response get pointer and a response put pointer;

wherein the host side increments the command put pointer in order to post the EMP command frame in the command ring and increments the response get pointer in order to release an entry in the response ring;

wherein the host side reads the command get pointer and response put pointer with both the command get pointer and the response put pointer having been updated by the memory device side prior to the memory device side posting the EMP response frame in the response ring and releasing an entry in the command ring; and

wherein the memory device side increments the command get pointer and the response put pointer prior to the memory device side posting the EMP response frame in the response ring and releasing the entry in the command ring;

exposing, to the host side, a first memory region in the memory device side, wherein the first memory region comprises configuration settings of the memory device side; and

exposing, to the host side, a second memory region in the memory device side, wherein the second memory region comprises at least a set of registers of the memory side device.

2. The method of claim 1, wherein the non-volatile memory in the memory device side comprises at least one solid state drive (SSD).

3. The method of claim 1, wherein the command frame and response frame comprise are SCSI-compliant (Small Computer System Interface compliant) frames.

4. The method of claim 1, wherein the command frame and response frame are transmitted across a PCIe (Peripheral Component Interconnect Express) bus.

5. The method of claim 1, further comprising:

placing, by the host side, a mailbox command in a mailbox memory of the memory device side, in order to inform the memory device side of the command frame for processing by the memory device side;

wherein the mailbox memory is sized to hold the mailbox command.

6. The method of claim 5, further comprising:

placing, by the memory side device, a mailbox response in the mailbox memory after the memory device side has processed the command frame.

7. An apparatus, comprising:

a host side configured to transmit an exchange message protocol (EMP) command frame to a memory device side;

wherein the host side is configured to post the EMP command frame into a first memory array in the memory device side, wherein the host side is coupled by a bus to the memory device side;

wherein the memory device side comprises a non-volatile memory device;

wherein the host side is configured to inform the memory device side to process the command frame;

wherein the memory device side is configured to execute the command frame in response to the EMP command frame being posted into the first memory array;

wherein the memory device side is configured to post an EMP response frame into a second memory array in the memory device side in response to the EMP command frame being executed by the memory device side;

wherein the memory device side is configured to transmit the EMP response frame to the host side, in response to the EMP response frame being posted into the second memory array;

wherein the non-volatile memory device in the memory device side comprises a command ring comprising the first memory array and a response ring comprising the second memory array, and wherein the rings implement asynchronous communication between the host side and the memory device side and allow processing of multiple outstanding command frames and of multiple outstanding response frames;

wherein the command ring in the non-volatile memory device comprises a command get pointer and a command put pointer;

wherein the response ring comprises a response get pointer and a response put pointer;

wherein the host side increments the command put pointer in order to post the EMP command frame in the command ring and increments the response get pointer in order to release an entry in the response ring;

wherein the host side reads the command get pointer and response put pointer with both the command get pointer and the response put pointer having been updated by the memory device side prior to the memory device side posting the EMP response frame in the response ring and releasing an entry in the command ring; and

wherein the memory device side increments the command get pointer and the response put pointer prior to the memory device side posting the EMP response frame in the response ring and releasing an entry in the command ring;

wherein the host side is exposed to a first memory region in the memory device side, wherein the first memory region comprises configuration settings of the memory device side; and

wherein the host side is exposed to a second memory region in the memory device side, wherein the second memory region comprises at least a set of registers of the memory side device.

8. The apparatus of claim 7, wherein the non-volatile memory in the memory device side comprises at least one solid state drive (SSD).

9. The apparatus of claim 7, wherein the command frame and response frame comprise are SCSI-compliant (Small Computer System Interface compliant) frames.

10. The apparatus of claim 7, wherein the command frame and response frame are transmitted across a PCIe (Peripheral Component Interconnect Express) bus.

11. The apparatus of claim 7, wherein the host side is configured to place a mailbox command in a mailbox memory of the memory device side, in order to inform the memory device side of the command frame for processing by the memory device side;

wherein the mailbox memory is sized to hold the mailbox command.

12. The apparatus of claim 11, wherein the memory side device is configured to place a mailbox response in the mailbox memory after the memory device side has processed the command frame.

13. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising;

transmitting, by a host side, an exchange message protocol (EMP) command frame to a memory device side;

wherein said transmitting further comprises posting, by the host side, the EMP command frame into a first memory array in the memory device side, wherein the host side is coupled by a bus to the memory device side;

wherein the memory device side comprises a non-volatile memory device;

informing, by the host side, the memory device side to process the command frame;

executing, by the memory device side, the command frame in response to the EMP command frame being posted into the first memory array;

posting, by the memory device side, an EMP response frame into a second memory array in the memory device side in response to the EMP command frame being executed by the memory device side;

transmitting, by the memory device side, the EMP response frame to the host side, in response to the EMP response frame being posted into the second memory array;

wherein the non-volatile memory device in the memory device side comprises a command ring comprising the first memory array and a response ring comprising the second memory array, and wherein the rings implement asynchronous communication between the host side and the memory device side and allow processing of multiple outstanding command frames and of multiple outstanding response frames;

wherein the command ring in the non-volatile memory device comprises a command get pointer and a command put pointer;

wherein the response ring comprises a response get pointer and a response put pointer;

wherein the host side increments the command put pointer in order to post the EMP command frame in the command ring and increments the response get pointer in order to release an entry in the response ring;

wherein the host side reads the command get pointer and response put pointer with both the command get pointer and the response put pointer having been updated by the memory device side prior to the memory device side posting the EMP response frame in the response ring and releasing an entry in the command ring; and

wherein the memory device side increments the command get pointer and the response put pointer prior to the memory device side posting the EMP response frame in the response ring and releasing an entry in the command ring;

exposing, to the host side, a first memory region in the memory device side, wherein the first memory region comprises configuration settings of the memory device side; and

exposing, to the host side, a second memory region in the memory device side, wherein the second memory region comprises at least a set of registers of the memory side device.

14. The article of manufacture of claim 13, wherein the command frame and response frame are transmitted across a PCIe (Peripheral Component Interconnect Express) bus.

15. The article of manufacture of claim 13, wherein the method further comprises:

placing, by the host side, a mailbox command in a mailbox memory of the memory device side, in order to inform the memory device side of the command frame for processing by the memory device side;

wherein the mailbox memory is sized to hold the mailbox command.