Array substrate, display panel and display device

• US 10,026,347 B2
• Filed: 03/31/2016
• Issued: 07/17/2018
• Est. Priority Date: 09/08/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Xu, Rui, Chen, Xiaochuan
• Primary Examiner(s): Kumar, Srilakshmi K
• Assistant Examiner(s): WILLS-BURNS, CHINEYERE D
• Application Number:
  US15/086,945
• Publication Number:
  US 20170069280A1
• Time in Patent Office: 838 Days
• Field of Search: 345100
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel and a display device, which may simplify bezels at three sides of the display panel and achieve the effect of almost zero bezel visually. Because a GOA design is not adopted, the cost of a drive circuit may be reduced, and poor relevant reliability caused by the GOA may be avoided. The array substrate comprises a display area and a drive circuit area. The display area includes: a plurality of pixel units, a plurality of data lines, and a plurality of gate lines. The drive circuit area includes: a drive module being configured to provide signals to data lines and gate lines. The drive circuit area is outside of the display area and close to the data lines. The embodiments of the present disclosure are used to manufacture the array substrate, the display panel and the display device.

Claims

1. An array substrate, comprising:

a display area; and

a drive circuit area;

wherein the display area includes;

a plurality of pixel units arranged in an array;

a plurality of data lines arranged in parallel with each other and connected to the plurality of pixel units; and

a plurality of gate lines arranged in parallel with each other and connected to the plurality of pixel units;

wherein the plurality of data lines intersects with the plurality of gate lines;

wherein the drive circuit area includes a drive circuit configured to provide data signals to the plurality of data lines and provide gate scanning signals to the plurality of gate lines, the drive circuit includes N first multiplexers each configured to output the gate scanning signals to X of the plurality of gate lines, the drive circuit includes a timing controller having X gate scanning signal output pins each connected to all of the N first multiplexers, a total number of the plurality of gate lines is X*N, and X and N are positive integers, greater than 1; and

wherein the drive circuit area is outside of the display area, is adjacent to one end of the data lines, and is not adjacent to ends of the gate lines.

2. The array substrate of claim 1, wherein each of the N first multiplexers comprises X first switching transistors each having first, second and control electrodes, the first electrodes of the X first switching transistors are connected to the X gate scanning signal output pins of the timing controller, the second electrodes are connected to the X gate lines, and the control electrodes are connected to a control circuit in the drive circuit.

3. The array substrate of claim 2, wherein each of the plurality of pixel units comprises X subpixel units arranged along a direction of the plurality of data lines.

4. The array substrate of claim 1, wherein the drive module comprises M second multiplexers, and each of the second multiplexers is configured to output the data signals to X of the plurality of data lines;

and wherein a total number of the plurality of data lines is X*M, and M is a positive integer greater than 1.

5. The array substrate of claim 4, wherein the timing controller includes X data signal output pins, and the X data signal output pins are connected to each of the M second multiplexers.

6. The array substrate of claim 5, wherein each of the M second multiplexers comprises X second switching transistors each having first, second and control electrodes, the first electrodes of the X second switching transistors are connected to the X data signal output pins of the timing controller, the second electrodes are connected to the X data lines, and the control electrodes are connected to a control circuit in the drive circuit.

7. The array substrate of claim 6, wherein each of the plurality of pixel units comprises X subpixel units arranged along a direction of the plurality of data lines.

8. The array substrate of claim 5, wherein each of the plurality of pixel units comprises X subpixel units arranged along a direction of the plurality of data lines.

9. The array substrate of claim 4, wherein each of the plurality of pixel units comprises X subpixel units arranged along a direction of the plurality of data lines.

10. The array substrate of claim 4, wherein X=3.

11. The array substrate of claim 1, wherein each of the plurality of pixel units comprises X subpixel units arranged along a direction of the plurality of data lines.

12. The array substrate of claim 1, wherein X=3.

13. A display panel, comprising the array substrate of claim 1.

14. The display panel of claim 13, wherein the drive circuit comprises M second multiplexers, and each of the second multiplexers is configured to output data signals to X of the plurality of data lines;

and wherein a total number of the plurality of data lines is X*M, and M is a positive integer greater than 1.

15. A display device, comprising the display panel of claim 13.