Method for controlling a display panel, a circuit of controlling a display panel and a display apparatus

• US 10,026,352 B2
• Filed: 08/04/2016
• Issued: 07/17/2018
• Est. Priority Date: 10/27/2015
• Status: Expired due to Fees

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Miao, Jinghua, Li, Mubing, Lu, Pengcheng, Chen, Xiaochuan, Chen, Chung-Chun, Dong, Xue
• Primary Examiner(s): Lee, Nicholas
• Assistant Examiner(s): STONE, ROBERT M
• Application Number:
  US15/228,574
• Publication Number:
  US 20170116910A1
• Time in Patent Office: 712 Days
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/2074 using sub-pixels
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes

Abstract

The application provides a method for controlling a display panel, a circuit of controlling a display panel and a display apparatus. The method comprise: classifying sub sets of sub pixels in a same row according to an arrangement of the gate lines, the sets of sub pixels and the multiplexers of the display panel; for each received frame of original image data, inserting gate control data according to different types of the sub sets of sub pixels, wherein a gate control data is inserted preceding the image displaying data corresponding to each sub set of sub pixels, for the image displaying data corresponding to the n^th row of sub pixels in each frame of the original image data, so as to generate sets of control and display data. The source driving circuit can apply signals corresponding to the data from the generated sets of control and display data to the corresponding multiplexers by using a time sharing method, based on the generated set of control and display data, so as to perform the displaying.

Claims

1. A method for controlling a display panel, the display panel comprises a plurality of sub pixels arranged in an array, N gate lines connected to each row of sub pixels respectively, data lines connected to each column of sub pixels and a plurality of multiplexers connected to N gate lines one by one, wherein m columns of neighboring sub pixels are grouped into a set of sub pixels, each of the plurality of multiplexers is connected to one set of sub pixels via the data lines, and different multiplexers are connected to different sets of sub pixels, wherein N and m are both integers greater than 0, wherein:

each row of sub pixels in each set of sub pixels is considered as a sub set of sub pixels, the sub sets of sub pixels in each row are classified to a first-type sub set of sub pixels and a plurality of second-type sub set of sub pixels, wherein in the n^th row of sub pixels, the first-type sub set of sub pixels is a sub set of sub pixels connected to the multiplexer which is connected with the n^th gate line, and the second-type sub sets of sub pixels are other sub sets of sub pixels other than the first-type sub set of sub pixels in the n^th row of sub pixels, wherein n is an integer and 1<

n≤

N;

the method comprising;

receiving an original image data, wherein each frame of the original image data comprises image displaying data corresponding to the plurality of sub pixels;

inserting a gate control data preceding the image displaying data corresponding to each sub set of sub pixels, for the image displaying data corresponding to the n^th row of sub pixels in each frame of the original image data, so as to generate sets of control and display data which correspond to each of the sub sets of sub pixels respectively;

wherein the gate control data inserted preceding the image displaying data corresponding to the first-type sub set of sub pixels is used for turning-on the gate line for the n^th row of sub pixels, and the gate control data inserted preceding the image displaying data corresponding to the second-type sub sets of sub pixels is used for turning-off the gate line for the n^th row of sub pixels; and

outputting a signal corresponding to a set of data from a corresponding set of control and display data to each of the multiplexers corresponding to the sub sets of sub pixels simultaneously in a same period, according to the sets of control and display data corresponding to the sub sets of sub pixels in the n^th row of sub pixels, upon displaying the n^th row of sub pixels by a source driving circuit; and

outputting the signal corresponding to the set of data from the corresponding set of control and display data to each of the multiplexers sequentially according to an arrangement of data from the sets of control and display data.

2. The method of claim 1, wherein the n^th set of sub pixels along an extension direction of the gate lines and the n^th gate line in the display panel correspond to a same multiplexer;

and

in the n^th row of sub pixels, the n^th sub set of sub pixels along an extension direction of the gate line is classified to the first-type sub set of sub pixels.

3. A circuit of controlling a display panel, the display panel comprises a plurality of sub pixels arranged in an array, N gate lines connected to each row of sub pixels respectively, data lines connected to each column of sub pixels and a plurality of multiplexers connected to N gate lines one by one, wherein m columns of neighboring sub pixels are grouped into a set of sub pixels, each of the plurality of multiplexers is connected to one set of sub pixels via the data lines, and different multiplexers are connected to different sets of sub pixels, wherein N and m are both integers greater than 0, wherein:

each row of sub pixels in each set of sub pixels is considered as a sub set of sub pixels, the sub sets of sub pixels in each row are classified to a first-type sub set of sub pixels and a plurality of second-type sub set of sub pixels, wherein in the n^th row of sub pixels, the first-type sub set of sub pixels is a sub set of sub pixels connected to the multiplexer which is connected with the n^th gate line, and the second-type sub sets of sub pixels are other sub sets of sub pixels other than the first-type sub set of sub pixels in the n^th row of sub pixels, wherein n is an integer and 1<

n≤

N;

the circuit comprising;

a data processing unit, configured to receive an original image data, wherein each frame of the original image data comprises image displaying data corresponding to the plurality of sub pixels; and

to insert a gate control data preceding the image displaying data corresponding to each sub set of sub pixels, for the image displaying data corresponding to the n^th row of sub pixels in each frame of the original image data, so as to generate sets of control and display data which correspond to each of the sub sets of sub pixels respectively;

wherein the gate control data inserted preceding the image displaying data corresponding to the first-type sub set of sub pixels is used for turning-on the gate line for the n^th row of sub pixels, and the gate control data inserted preceding the image displaying data corresponding to the second-type sub sets of sub pixels is used for turning-off of the gate line for the n^th row of sub pixels; and

a source driving circuit, configured to output a signal corresponding to a set of data from a corresponding set of control and display data to each of the multiplexers corresponding to the sub sets of sub pixels simultaneously in a same period, according to the sets of control and display data corresponding to the sub sets of sub pixels in the n^th row of sub pixels, upon controlling the displaying of the n^th row of sub pixels;

wherein the signal corresponding to the set of data from the corresponding set of control and display data is outputted to each of the multiplexers sequentially according to an arrangement of data from the sets of control and display data.

4. The circuit of claim 3, wherein the n^th set of sub pixels along an extension direction of the gate lines and the n^th gate line in the display panel correspond to a same multiplexer;

and

in the n^th row of sub pixels, the n^th sub set of sub pixels along an extension direction of the gate line is classified to the first-type sub set of sub pixels.

5. A display apparatus, comprising a display panel which comprises a plurality of sub pixels arranged in an array, N gate lines connected to each row of sub pixels respectively, data lines connected to each column of sub pixels and a plurality of multiplexers connected to N gate lines one by one, wherein m columns of neighboring sub pixels are grouped into a set of sub pixels, each of the plurality of multiplexers is connected to one set of sub pixels via the data lines, and different multiplexers are connected to different sets of sub pixels, wherein N and m are both integers greater than 0, wherein:

each row of sub pixels in each set of sub pixels is considered as a sub set of sub pixels, the sub sets of sub pixels in each row are classified to a first-type sub set of sub pixels and a plurality of second-type sub set of sub pixels, wherein in the n^th row of sub pixels, the first-type sub set of sub pixels is a sub set of sub pixels connected to the multiplexer which is connected with the n^th gate line, and the second-type sub sets of sub pixels are other sub sets of sub pixels other than the first-type sub set of sub pixels in the n^th row of sub pixels, and

the display apparatus further comprises the circuit of claim 3.

6. The display apparatus of claim 5, wherein the plurality of multiplexers are placed on a periphery of an area on the display panel which is pointed by an extension direction of the data lines.

7. The display apparatus of claim 5, wherein the display apparatus is a liquid crystal display panel.

8. The display apparatus of claim 6, wherein the display apparatus is a liquid crystal display panel.