Content addressable memory device having electrically floating body transistor
First Claim
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1. A content addressable memory cell comprising:
- a first bipolar device having a floating base region, a collector, and an emitter;
a second bipolar device having a floating base region, a collector, and an emitter; and
a transistor;
wherein said first bipolar device and said second bipolar device are electrically connected in series through a common node;
wherein a gate of said transistor is electrically connected to said common node; and
wherein said first bipolar device is configured to store first data and said second bipolar device is configured to simultaneously store second data that is complementary to said first data.
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Abstract
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
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Citations
20 Claims
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1. A content addressable memory cell comprising:
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a first bipolar device having a floating base region, a collector, and an emitter; a second bipolar device having a floating base region, a collector, and an emitter; and a transistor; wherein said first bipolar device and said second bipolar device are electrically connected in series through a common node; wherein a gate of said transistor is electrically connected to said common node; and wherein said first bipolar device is configured to store first data and said second bipolar device is configured to simultaneously store second data that is complementary to said first data. - View Dependent Claims (2, 3, 4, 5)
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6. A content addressable memory cell comprising:
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a first bi-stable bipolar device having a floating base region, a collector, and an emitter; a second bi-stable bipolar device having a floating base region, a collector, and an emitter; and a transistor; wherein said first bi-stable bipolar device and said second bi-stable bipolar device are electrically connected in series through a common node; wherein a gate of said transistor is electrically connected to said common node; and wherein said first bi-stable bipolar device is configured to store first data and said second bi-stable bipolar device is configured to simultaneously store second data that is complementary to said first data. - View Dependent Claims (7, 8, 9)
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10. A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:
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a first bipolar device having a floating base region, a collector, and an emitter; a second bipolar device having a floating base region, a collector, and an emitter; and a transistor; wherein said first bipolar device and said second bipolar device are electrically connected in series through a common node; wherein a gate of said transistor is electrically connected to said common node; and wherein said first bipolar device is configured to store first data and said second bipolar device is configured to simultaneously store second data that is complementary to said first data. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification