Content addressable memory device having electrically floating body transistor

• US 10,026,479 B2
• Filed: 09/28/2015
• Issued: 07/17/2018
• Est. Priority Date: 01/14/2013
• Status: Active Grant

• Current Assignee: Law Office of Alan W. Cannon, Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Louie, Benjamin S., Han, Jin-Woo, Widjaja, Yuniarto
• Primary Examiner(s): Mai, Son
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US14/867,308
• Publication Number:
  US 20170092359A1
• Time in Patent Office: 1,023 Days
• Field of Search: 365 4917
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Claims

1. A content addressable memory cell comprising:

a first bipolar device having a floating base region, a collector, and an emitter;

a second bipolar device having a floating base region, a collector, and an emitter; and

a transistor;

wherein said first bipolar device and said second bipolar device are electrically connected in series through a common node;

wherein a gate of said transistor is electrically connected to said common node; and

wherein said first bipolar device is configured to store first data and said second bipolar device is configured to simultaneously store second data that is complementary to said first data.

2. The content addressable memory cell of claim 1, wherein said first bipolar device and said second bipolar device comprise a buried well region.

3. The content addressable memory cell of claim 1, wherein said first bipolar device and said second bipolar device comprise a buried insulator region.

4. The content addressable memory cell of claim 1, wherein said first bipolar device comprises a first gate region and said second bipolar device comprises a second gate region.

5. The content addressable memory cell of claim 1, wherein said transistor comprises a floating body transistor.

6. A content addressable memory cell comprising:

a first bi-stable bipolar device having a floating base region, a collector, and an emitter;

a second bi-stable bipolar device having a floating base region, a collector, and an emitter; and

a transistor;

wherein said first bi-stable bipolar device and said second bi-stable bipolar device are electrically connected in series through a common node;

wherein a gate of said transistor is electrically connected to said common node; and

wherein said first bi-stable bipolar device is configured to store first data and said second bi-stable bipolar device is configured to simultaneously store second data that is complementary to said first data.

7. The content addressable memory cell of claim 6, wherein said first bi-stable bipolar device and said second bi-stable bipolar device comprise a buried well region.

8. The content addressable memory cell of claim 6, wherein said first bi-stable bipolar device comprises a first gate region and said second bi-stable bipolar device comprises a second gate region.

9. The content addressable memory cell of claim 6, wherein said transistor comprises a floating body transistor.

10. A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:

a first bipolar device having a floating base region, a collector, and an emitter;

a second bipolar device having a floating base region, a collector, and an emitter; and

a transistor;

wherein said first bipolar device and said second bipolar device are electrically connected in series through a common node;

wherein a gate of said transistor is electrically connected to said common node; and

wherein said first bipolar device is configured to store first data and said second bipolar device is configured to simultaneously store second data that is complementary to said first data.

11. The content addressable memory array of claim 10, wherein said first bipolar device and said second bipolar device comprise a buried well region.

12. The content addressable memory array of claim 10, wherein said first bipolar device and said second bipolar device comprise a buried insulator region.

13. The content addressable memory array of claim 10, wherein said first bipolar device comprises a first gate region and said second bipolar device comprises a second gate region.

14. The content addressable memory array of claim 10, wherein said transistor comprises a floating body transistor.

15. The content addressable memory array of claim 10, wherein said transistor is connected to a match detection line.

16. The content addressable memory array of claim 15, wherein said match detection line is connected to a pull-up device or a power source at a first end portion of said match detection line.

17. The content addressable memory array of claim 16, wherein said match detection line is connected to a match detection node at a second end portion of said match detection line.

18. The content addressable memory array of claim 15, wherein said match detection line is pre-conditioned to a low logic state.

19. The content addressable memory array of claim 15, wherein said match detection line is configured to propagate a high logic state when a predetermined match condition is satisfied.

20. The content addressable memory array of claim 15, wherein said match detection line is configured to remain at a low logic state when a predetermined match condition is not satisfied.