Memory device including multiple select gates and different bias conditions

• US 10,026,480 B2
• Filed: 08/04/2017
• Issued: 07/17/2018
• Est. Priority Date: 07/08/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Liu, Haitao, Lee, Changhyun
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US15/669,311
• Publication Number:
  US 20180012660A1
• Time in Patent Office: 347 Days
• Field of Search: 36518511, 36518524
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

Claims

1. An apparatus comprising:

a pillar extending between a conductive material region and a source, the pillar including a first segment, a second segment, and a third segment, the second segment being between the first and third segments;

a first select gate located along the first segment of the pillar and including a conductive material having sidewall at a first distance from the first segment of the pillar;

a second select gate located along the second segment of the pillar and including a conductive material having a sidewall at a second distance from the second segment of the pillar; and

a memory cell string and a plurality of conductive materials located along the third segment of the pillar, each conductive material of the plurality of conductive materials including sidewall at a third distance from the third segment of the pillar, the third distance being different from each of the first and second distances, the first and second select gates to receive voltages having different values during an operation of the apparatus.

2. The apparatus of claim 1, further comprising an additional memory cell string coupled to an additional plurality of conductive materials, the additional plurality of conductive materials being different from the plurality of conductive materials located along the third segment of the pillar, wherein the operation includes one of an operation of storing information in a memory cell of the additional memory cell string and an operation of reading information from a memory cell of the additional memory cell string, and the plurality of conductive materials are part of first control lines of the apparatus, and the additional plurality of conductive materials are part of second control lines of the apparatus.

3. The apparatus of claim 1, further comprising an additional memory cell string, wherein the plurality of conductive materials are part of control lines of the apparatus, the additional memory cell string share the control lines with the memory cell string located along the third segment of the pillar, and the operation includes one of an operation of storing information in a memory cell of the additional memory cell string and an operation of reading information from a memory cell of the additional memory cell string.

4. The apparatus of claim 1, wherein the operation includes erasing information from memory cells of the memory cell string.

5. The apparatus of claim 1, wherein the third distance is greater than each of the first and second distances.

6. The apparatus of claim 1, wherein the first select gate is between the conductive material region and the memory cell string, and the conductive material region is part of a data line of the apparatus.

7. The apparatus of claim 1, wherein the first select gate is between the memory cell string and the source.

8. The apparatus of claim 1, wherein at least one of the first and second select gates includes a metal portion.

9. The apparatus of claim 1, wherein at least one of the first and second select gates includes a silicide portion.

10. An apparatus comprising:

a pillar extending between a conductive material region and a source, the pillar including a first segment, a second segment, and a third segment, the second segment being between the first and third segments;

a first select gate located along the first segment of the pillar, the first select gate including a conductive material having a first thickness;

a second select gate located along the second segment of the pillar;

the second select gate including a conductive material having a second thickness, the first thickness being greater than the second thickness; and

a memory cell string and control lines located along the third segment of the pillar.

11. The apparatus of claim 10, wherein the pillar includes a first material of a first conductivity type and a second material of a second conductive type, the first material contacting the second material at a location in the first segment of the pillar.

12. The apparatus of claim 11, wherein the first conductivity type includes n-type, and the second conductive type includes p-type.

13. The apparatus of claim 10, wherein the conductive material of at least one of the first and second select gates includes a metal portion.

14. The apparatus of claim 10, wherein the conductive material of at least one of the first and second select gates includes a silicide portion.

15. The apparatus of claim 10, wherein the conductive material of at least one of the first and second select gates includes a first portion and a second portion, the first portion is between the pillar and the second portion, the first portion includes polycrystalline silicon, and the second portion includes one of metal and silicide.

16. The apparatus of claim 10, wherein the first and second select gates are to receive voltages having different values during an operation of the apparatus.

17. An apparatus comprising:

a pillar extending between a conductive material region and a source;

a first select gate located along a first segment of the pillar, the first select gate including a first conductive portion and a second conductive portion contacting the first conductive portion, the first and second conductive portions having different resistances;

a second select gate located along a second segment of the pillar;

the second select gate including a first conductive portion and a second conductive portion contacting the first conductive portion of the second select gate, the first and second conductive portions of the second select gate having different resistances; and

a memory cell string and control lines located along a third segment of the pillar.

18. The apparatus of claim 17, wherein in at least one of the first select gate and the second select gate, the first conductive portion is a polycrystalline silicon portion and the second conductive portion is a metal portion.

19. The apparatus of claim 17, wherein in at least one of the first select gate and the second select gate, the first conductive portion is a polycrystalline silicon portion and the second conductive portion is a silicide portion.

20. The apparatus of claim 17, wherein at least one conductive line of the control lines includes a first conductive portion and a second conductive portion contacting the first conductive portion of the at least one conductive line, the first and second conductive portions of the at least one conductive line having different resistances.

21. The apparatus of claim 17, wherein the second conductive portion of the at least one conductive line includes is either a metal portion or a silicide portion.

22. The apparatus of claim 17, wherein the first and second select gates are to receive voltages having different values during an operation of the apparatus.