DRAM structure with a single diffusion break

• US 10,026,740 B1
• Filed: 10/30/2017
• Issued: 07/17/2018
• Est. Priority Date: 10/30/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zang, Hui, Ciavatti, Jerome, Watts, Josef
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US15/797,533
• Time in Patent Office: 260 Days
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H10B 12/02 for one transistor one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

One illustrative DRAM structure disclosed herein includes a first memory cell pair, a second memory cell pair, a single diffusion break (SDB) isolation structure positioned between the first and second memory cell pairs, and a single first gate positioned between the first and second memory cell pairs and above the SDB isolation structure.

Claims

1. A DRAM structure, comprising:

a first memory cell pair;

a second memory cell pair;

a single diffusion break (SDB) isolation structure positioned between said first memory cell pair and said second memory cell pair; and

a single first gate positioned between said first memory cell pair and said second memory cell pair and above said SDB isolation structure.

2. The DRAM structure of claim 1, wherein said SDB isolation structure comprises a lower portion positioned in a trench formed in a semiconductor substrate and an upper portion positioned above an upper surface of said semiconductor substrate, wherein a bottom surface of said upper portion of said SDB isolation structure is positioned on and in contact with an upper surface of said semiconductor substrate.

3. The DRAM structure of claim 1, wherein said SDB isolation structure has a generally rectangular configuration when viewed from above.

4. The DRAM structure of claim 1, wherein said single first gate is positioned on and in contact with said SDB isolation structure.

5. The DRAM structure of claim 1, wherein each of said first memory cell pair and said second memory cell pair comprise first and second memory cells, and wherein each of said first and second memory cells comprise one transistor and one capacitor.

6. The DRAM structure of claim 1, wherein:

said first memory cell pair comprises a first memory cell and a second memory cell, said first memory cell comprising a first transistor and a first capacitor, said second memory cell comprising a second transistor and a second capacitor, wherein second and third gates are positioned between said first and second capacitors; and

said second memory cell pair comprises a third memory cell and a fourth memory cell, said third memory cell comprising a third transistor and a third capacitor, said fourth memory cell comprising a fourth transistor and a fourth capacitor, wherein fourth and fifth gate structures are positioned between said third and fourth capacitors.

7. The DRAM structure of claim 6, wherein said first transistor and said second transistors share a first source/drain region that is adapted to be coupled to a first bit line and said third and fourth transistors share a second source/drain region that is adapted to be coupled to a second bit line.

8. The DRAM structure of claim 6, wherein said SDB isolation structure is positioned between said first capacitor within said first memory cell pair and said second capacitor within said second memory cell pair.

9. The DRAM structure of claim 1, wherein said SDB isolation structure has a dimension in a direction corresponding to a gate length direction of a transistor in said first memory cell pair that is greater than a dimension of said single first gate in said direction corresponding to said gate length direction of said transistor in said first memory cell pair.

10. The DRAM structure of claim 1, further comprising:

a third memory cell pair; and

a fourth memory cell pair, wherein said SDB isolation structure is positioned between said third memory cell pair and said fourth memory cell pair and wherein said single first gate is positioned between said third memory cell pair and said fourth memory cell pair and above said SDB isolation structure.

11. The DRAM structure of claim 1, further comprising a second SDB isolation structure positioned under said single first gate structure, said second SDB isolation structure being spaced apart from and separate from said SDB isolation structure.

12. The DRAM structure of claim 1, wherein said SDB isolation structure comprises silicon dioxide.

13. A DRAM structure, comprising:

a first memory cell pair;

a second memory cell pair positioned laterally adjacent said first memory cell pair;

a third memory cell pair;

a fourth memory cell pair positioned laterally adjacent said third memory cell pair;

a single diffusion break (SDB) isolation structure positioned between said first memory cell pair and said second memory cell pair and between said third memory cell pair and said fourth memory cell pair, wherein said SDB isolation structure comprises a lower portion positioned in a trench formed in a semiconductor substrate and an upper portion positioned above an upper surface of said semiconductor substrate, wherein a bottom surface of said upper portion of said SDB isolation structure is positioned on and in contact with said upper surface of said semiconductor substrate; and

a single first gate positioned above said SDB isolation structure and between said first memory cell pair and said second memory cell pair and between said third memory cell pair and said fourth memory cell pair.

14. The DRAM structure of claim 13, wherein each of said first, second, third and fourth memory cell pairs comprise first and second memory cells, and wherein each of said first and second memory cells comprise one transistor and one capacitor.

15. The DRAM structure of claim 13, wherein:

said first memory cell pair comprises a first memory cell and a second memory cell, said first memory cell comprising a first transistor and a first capacitor, said second memory cell comprising a second transistor and a second capacitor, wherein second and third gates are positioned between said first and second capacitors; and

said second memory cell pair comprises a third memory cell and a fourth memory cell, said third memory cell comprising a third transistor and a third capacitor, said fourth memory cell comprising a fourth transistor and a fourth capacitor, wherein fourth and fifth gate structures are positioned between said third and fourth capacitors.

16. The DRAM structure of claim 15, wherein said first transistor and said second transistor share a first source/drain region that is adapted to be coupled to a first bit line and said third transistor and said fourth transistor share a second source/drain region that is adapted to be coupled to a second bit line.

17. The DRAM structure of claim 16, wherein said SDB isolation structure is positioned between said first capacitor within said first memory cell pair and said second capacitor within said second memory cell pair.

18. The DRAM structure of claim 17, wherein said SDB isolation structure has a dimension in a direction corresponding to a gate length direction of said transistor in said first memory cell pair that is greater than a dimension of said single first gate in said direction corresponding to said gate length direction of said transistor in said first memory cell pair.

19. The DRAM structure of claim 15, further comprising a second SDB isolation structure positioned under said single first gate structure, said second SDB isolation structure being spaced apart from and separate from said SDB isolation structure.