Integrated circuit structure and method with solid phase diffusion

• US 10,026,811 B2
• Filed: 02/06/2017
• Issued: 07/17/2018
• Est. Priority Date: 06/23/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fang, Ziwei, Wang, Tsan-Chun
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US15/424,979
• Publication Number:
  US 20170148879A1
• Time in Patent Office: 526 Days
• Field of Search: 438548, 438559, 438751, 438757
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/31 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After treatment of these layers; Selection of materials for these layers
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/365 Planar doping, e.g. atomic-plane doping, delta-doping
• CPC Class Codes: H01L 29/66537 : using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 : with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate

Abstract

A method includes forming fin semiconductor features on a substrate. A dopant-containing dielectric material layer is formed on sidewalls of the fin semiconductor features and the substrate. A precise material modification (PMM) process is performed to the dopant-containing dielectric material layer. The PMM process includes forming a first dielectric material layer over the dopant-containing dielectric material layer; performing a tilted ion implantation to the first dielectric material layer so that a top portion of the first dielectric material layer is doped to have a modified etch characteristic different from an etch characteristic of a bottom portion of the first dielectric material layer; and performing an etch process to selectively remove the top portion of the first dielectric material layer and the top portion of the dopant-containing dielectric material layer.

Claims

1. A method, comprising:

forming fin semiconductor features on a substrate;

forming a dopant-containing dielectric material layer on sidewalls of the fin semiconductor features and the substrate;

performing a precise material modification (PMM) process to the dopant-containing dielectric material layer, wherein the PMM process includes;

forming a first dielectric material layer over the dopant-containing dielectric material layer;

performing a tilted ion implantation to the first dielectric material layer so that a top portion of the first dielectric material layer is doped to have a modified etch characteristic different from an etch characteristic of a bottom portion of the first dielectric material layer; and

performing an etch process to selectively remove the top portion of the first dielectric material layer and a top portion of the dopant-containing dielectric material layer.

2. The method of claim 1, wherein the first dielectric material layer includes a silicon nitride (SiN) layer.

3. The method of claim 1, wherein the forming the dopant-containing dielectric material layer includes:

depositing a dopant-containing silicate glass layer.

4. The method of claim 3, wherein the depositing the dopant-containing silicate glass layer includes:

forming one of a phosphosilicate glass (PSG) layer and a borosilicate glass (BSG) layer.

5. The method of claim 3, wherein the forming the dopant-containing dielectric material layer includes:

forming an un-doped silicate glass (USG) layer on the dopant-containing silicate glass layer.

6. The method of claim 1, further comprising:

removing the bottom portion of the first dielectric material layer after the performing the etch process; and

forming a second dielectric material layer over the bottom portion of the dopant-containing dielectric material layer.

7. The method of claim 1, further comprising:

after the performing PMM process, performing a first ion implantation to the substrate, thereby forming a doped well of a first type conductivity with a well carrier concentration;

performing a second ion implantation to top portions of the fin semiconductor features, thereby forming channel regions of the first type conductivity with a channel carrier concentration less than the well carrier concentration; and

performing a thermal annealing process to diffuse a first type dopant from the bottom portion of the dopant-containing dielectric material layer to bottom portions of the fin semiconductor features, thereby forming anti-punch-through (APT) features of the first type conductivity with an APT carrier concentration greater than the well carrier concentration.

8. A method, comprising:

providing a substrate including a plurality of fin elements;

depositing a dopant-containing dielectric material layer over sidewalls of the plurality of fin elements and the substrate;

forming a first dielectric material layer over the dopant-containing dielectric material layer;

modifying a top portion of the first dielectric material layer so that the top portion of the first dielectric material layer has a first etching characteristic different from a second etch characteristic of a bottom portion of the first dielectric material layer; and

performing a first etch process to selectively remove the top portion of the first dielectric material layer and a top portion of the dopant-containing dielectric material layer, thereby exposing sidewalls of top portions of the plurality of fin elements.

9. The method of claim 8, wherein the modifying the top portion of the first dielectric material layer includes:

performing a tilted ion implantation to the first dielectric material layer so that the top portion of the first dielectric material layer is doped by the tilted ion implantation.

10. The method of claim 8, wherein the depositing the dopant-containing dielectric material layer includes:

forming a dopant-containing silicate glass layer; and

forming an un-doped silicate glass (USG) layer on the dopant-containing silicate glass layer.

11. The method of claim 10, further comprising:

after performing the first etch process, performing a second etch process, thereby removing the bottom portion of the first dielectric material layer and exposing a top surface of the USG layer, wherein the USG layer has a concave profile.

12. The method of claim 11, further comprising:

forming a second dielectric material layer over the bottom portion of the dopant-containing dielectric material layer.

13. The method of claim 12, further comprising:

performing a first ion implantation to the substrate, thereby forming a doped well of a first type conductivity with a well carrier concentration;

performing a second ion implantation to the top portions of the plurality of fin elements, thereby forming channel regions of the first type conductivity with a channel carrier concentration less than the well carrier concentration; and

performing a thermal annealing process to diffuse a first type dopant from the bottom portion of the dopant-containing dielectric material layer to bottom portions of the plurality of fin elements, thereby forming anti-punch-through (APT) features of the first type conductivity with an APT carrier concentration greater than the well carrier concentration.

14. The method of claim 13, further comprising:

removing a top portion of the second dielectric material layer, thereby exposing the top portions of the plurality of fin elements;

forming first gate stacks over the top portions of the plurality of fin elements;

forming source and drain features adjacent to the first gate stacks; and

performing a gate replacement process to replace the first gate stacks with metal gate stacks.

15. A method, comprising:

providing a substrate including a first region having a first plurality of fin elements and a second region having a second plurality of fin elements;

forming a first dopant-containing dielectric layer containing a first-type dopant over the first region;

forming a second dopant-containing dielectric layer containing a second-type dopant opposite to the first-type dopant over the second region;

depositing a first dielectric material layer over the first dopant-containing dielectric layer in the first region and the second dopant-containing dielectric layer in the second region;

modifying a top portion of the first dielectric material layer so that the top portion of the first dielectric material layer has a first etching characteristic different from a second etch characteristic of a bottom portion of the first dielectric material layer; and

performing a first etch process to selectively remove the top portion of the first dielectric material layer, a first top portion of the first dopant-containing dielectric material layer, and a second top portion of the second dopant-containing dielectric material layer.

16. The method of claim 15, wherein the forming the first dopant-containing dielectric layer includes:

forming one of a phosphosilicate glass (PSG) layer and a borosilicate glass (BSG) layer; and

wherein the forming the second dopant-containing dielectric layer includes;

forming the other of the PSG layer and the BSG layer.

17. The method of claim 15, further comprising:

performing a second etch process to remove the bottom portion of the first dielectric material layer in the first region and the second region.

18. The method of claim 17, further comprising:

performing a first ion implantation to the first region, thereby forming a first doped well of a first type conductivity with a first concentration; and

performing a second ion implantation to top portions of the first plurality of fin elements, thereby forming channel regions of the first type conductivity with a second concentration less than the first concentration.

19. The method of claim 18, further comprising:

performing a third ion implantation to the second region, thereby forming a second doped well of a second type conductivity with a third concentration; and

performing a fourth ion implantation to top portions of the second plurality of fin elements, thereby forming channel regions of the second type conductivity with a fifth concentration less than the fourth carrier concentration.

20. The method of claim 19, further comprising:

performing a thermal annealing process,

wherein the first type dopant is diffused from the bottom portion of the first dopant-containing dielectric material layer to the bottom portions of the first plurality of fin elements, thereby forming first-type anti-punch-through (APT) features of the first type conductivity with a sixth concentration greater than the first carrier concentration; and

wherein the second type dopant is diffused from the bottom portion of the second dopant-containing dielectric material layer to the bottom portions of the second plurality of fin elements, thereby forming second-type APT features of the second type conductivity with a seventh concentration greater than the fourth concentration.