Field boosted metal-oxide-semiconductor field effect transistor

• US 10,026,835 B2
• Filed: 06/25/2010
• Issued: 07/17/2018
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Tipirneni, Naveen, Pattanayak, Deva
• Primary Examiner(s): AHMED, SELIM U
• Application Number:
  US12/824,075
• Publication Number:
  US 20110095359A1
• Time in Patent Office: 2,944 Days
• Field of Search: 257329-334, 257344, 257408, 257E2706
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions.

Claims

1. A trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising:

a drain region;

a plurality of gate regions disposed above the drain region;

a plurality of drift regions disposed in mesas between the plurality of gate regions and above the drain region;

a plurality of body regions disposed in the mesas, above the plurality of drift regions, and disposed at substantially the same depth as from top to bottom of adjacent plurality of gate regions;

a plurality of source regions disposed in the mesas above the plurality of body regions;

a plurality of gate insulator regions, including;

a thin portion disposed between the plurality of gate regions and the plurality of body regions,

a thick portion disposed between the plurality of gate regions and the plurality of drift regions substantially the depth from the top to the bottom of the plurality of drift regions and between the plurality of gate regions and the drain region;

wherein the width of at least one of the mesas is approximately 0.03 to 1.0 microns (μ

m) and is in the order of quantum well dimension at the interface between the plurality of gate insulator regions and the plurality of body regions; and

wherein a thickness of the plurality of gate insulator regions directly between the plurality of gate regions and the drain region is approximately 0.1to 4.0 microns (μ

m) and is selected so that the gate-to-drain electric field in the OFF-state of the device is substantially lateral in the plurality of drift regions and impacts the breakdown voltage.

2. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein the plurality of drift regions comprise a graded doping profile decreasing vertically from the drain region to the plurality of body regions or varying laterally from edges of one of the mesas to a center of another of the mesas.

3. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein a p-n junction is formed in the mesas using the drain region.

4. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein the plurality of source regions and the plurality of body regions are coupled at substantially the same electrical potential.

5. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein doping of the plurality of drift regions have a p-n junction breakdown voltage degradation less than that predicted by planar p-n junction theory.

6. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein a relationship between breakdown voltage of a p-n junction in the mesas and a doping in the mesas is controlled by the width of the mesas.

7. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein a fringing field between the gate regions and the drain region in an OFF-state aid in depleting a charge in the plurality of drift regions in the mesas allowing a higher doping in the plurality of drift regions for a substantially constant breakdown voltage.

8. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein the thickness of the plurality of gate insulator regions between the plurality of gate regions and the drain region provides for a substantially constant breakdown voltage even for an increased drift region doping concentration without adding additional gate charge, which results in a low ON-resistance gate charge product.

9. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein:

the drain region comprises a heavily n-doped semiconductor;

the plurality of gate regions comprise an n-doped semiconductor;

the plurality of drift regions comprise a lightly n-doped semiconductor;

the plurality of body regions comprise a moderately p-doped semiconductor; and

the plurality of source regions comprise a heavily n-doped semiconductor.

10. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein:

the drain region comprises a heavily n-doped semiconductor;

the plurality of gate regions comprise an n-doped semiconductor;

the plurality of drift regions comprise a lightly to moderately n-doped semiconductor from the body regions to the drain region;

the plurality of body regions comprise a moderately p-doped semiconductor; and

the plurality of source regions comprise a heavily n-doped semiconductor.

11. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 1, wherein the plurality of gate insulator regions comprise an oxide.

12. A trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising:

a drain region;

at least one gate region;

at least one mesa, each including a drift region and a body region; and

at least one gate insulator region, including;

a thin portion disposed between at least one of the gate regions and at least one of the body regions,

a thick portion disposed between at least one of the gate regions and at least one of the drift regions substantially the depth from the top to the bottom of at least one of the drift regions and between at least one of the gate regions and at least one of the drain regions, wherein a thickness of at least one of the gate insulator regions directly between at least one of the gate regions and the drain region is approximately 0.1 to 4.0 microns (μ

m) and is selected so that the gate-to-drain electric field in the OFF- state of the device is substantially lateral in at least one of the drift regions and impacts the breakdown voltage;

wherein the width of each mesa is approximately 0.03 to 1.0 microns (μ

m) and is in the order of quantum well dimension at the interface between at least one of the gate insulator regions and at least one of the body regions.

13. The trench metal-oxide-semiconductor field effect transistor) of claim 12, wherein the gate insulator regions comprise an oxide.

14. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 12, wherein:

the drain region comprises silicon heavily doped with phosphorous or arsenic;

the drift regions comprise silicon lightly or moderately doped with phosphorous or arsenic; and

the body regions comprise silicon lightly or moderately doped with boron.

15. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 14, wherein the drift regions comprise a graded doping profile decreasing from the drain region to the body regions.

16. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 14, wherein a doping concentration of the drift regions is approximately 5.00E+14 to 8.00E+17 per cubic centimeters.

17. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 16, wherein the width of the mesas is approximately 0.03 to 2.0 microns (um).

18. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 17, wherein the thickness of the gate insulator regions between the gate regions and the drain region is approximately 0.1 to 4.0 microns (um).

19. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 18, wherein a breakdown voltage is approximately 15V to 55V.

20. The trench metal-oxide-semiconductor field effect transistor (TMOSFET) of claim 18, wherein a ON-state resistant is approximately 2 to 9 milli-ohms per square millimeter (mohm.mm2).