Fin structure of semiconductor device, manufacturing method thereof, and manufacturing method of active region of semiconductor device

• US 10,026,843 B2
• Filed: 11/30/2015
• Issued: 07/17/2018
• Est. Priority Date: 11/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Che-Yu, Yu, Ming-Hua, Lee, Tze-Liang, Yang, Chan-Lon
• Primary Examiner(s): Hossain, Moazzam
• Application Number:
  US14/954,661
• Publication Number:
  US 20170154996A1
• Time in Patent Office: 960 Days
• Field of Search: 257401
• CPC Class Codes: H01L 21/02057 Cleaning during device manufacture
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method for manufacturing an active region of a semiconductor device includes forming an implanted region in a substrate. The implanted region is adjacent to a top surface of the substrate. A clean treatment is performed on the top surface of the substrate. The top surface of the substrate is baked. An epitaxial layer is formed on the top surface of the substrate.

Claims

1. A fin structure of a semiconductor device comprising:

a substrate having an implanted region with a depth less than a depth of the substrate and a plurality of trenches therein, wherein the trenches define at least one bottom fin portion comprising at least a portion of the implanted region; and

an epitaxial fin portion disposed on a top surface of the bottom fin portion, wherein the implanted region of the substrate comprises oxygen and has an oxygen concentration lower than about 1.E+18 atoms/cm³.

2. The fin structure of claim 1, wherein the implanted region comprises boron (B), phosphor (P), or a combination thereof.

3. The fin structure of claim 1, further comprising:

an isolation structure disposed in at least one of the trenches.

4. The fin structure of claim 3, wherein the epitaxial fin portion is higher than the isolation structure.

5. The fin structure of claim 3, wherein the top surface of the bottom fin portion is lower than the isolation structure.

6. The fin structure of claim 1, wherein the substrate is made of silicon.

7. The fin structure of claim 1, wherein the epitaxial fin portion is made of silicon.

8. The fin structure of claim 3, further comprising a liner layer disposed between the substrate and the isolation structure.

9. The fin structure of claim 8, wherein the liner layer is in contact with the implanted region of the substrate.

10. The fin structure of claim 1, wherein the epitaxial fin portion is in contact with the implanted region of the substrate.

11. A fin structure of a semiconductor device comprising

a substrate having at least one bottom fin portion thereon formed of an implanted region of the substrate, the implanted region having a depth less than a depth of the substrate;

an isolation structure surrounding the bottom fin portion; and

an epitaxial fin portion disposed on a top surface of the bottom fin portion, wherein an interface between the epitaxial fin portion and the bottom fin portion comprises oxygen and has an oxygen concentration lower than about 1.E+19 atoms/cm³.

12. The fin structure of claim 11, wherein the bottom fin portion comprises boron (B), phosphor (P), or a combination thereof.

13. The fin structure of claim 11, wherein the isolation structure is in a position lower than the epitaxy fin portion.

14. The fin structure of claim 11, further comprising a liner layer disposed between the isolation structure and the substrate.

15. The fin structure of claim 11, wherein a top surface of the isolation structure is in a position higher than the top surface of the bottom fin portion of the substrate.

16. The fin structure of claim 11, wherein the substrate and the epitaxial fin portion are made of the same material.

17. A fin structure of a semiconductor device comprising

a substrate having a plurality of bottom fin portions thereon;

an isolation structure between the bottom fin portions; and

a plurality of epitaxial fin portions disposed on the bottom fin portions respectively, wherein the bottom fin portions are formed of an implanted region of the substrate, comprise oxygen, and have an oxygen concentration lower than about 1.E+18 atoms/cm³, the implanted region having a depth less than a depth of the substrate.

18. The fin structure of claim 17, wherein a top surface of the isolation structure is in a position lower than top surfaces of the epitaxial fin portions.

19. The fin structure of claim 17, wherein a top surface of the isolation structure is in a position higher than interfaces of the bottom fin portions and the epitaxial fin portions.

20. The fin structure of claim 17, wherein the substrate and the epitaxial fin portions are made of silicon.