Semiconductor device

• US 10,026,848 B2
• Filed: 05/31/2016
• Issued: 07/17/2018
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi
• Primary Examiner(s): MA, CALVIN
• Application Number:
  US15/168,293
• Publication Number:
  US 20160276490A1
• Time in Patent Office: 777 Days
• Field of Search: 345 87, 345205, 345690
• CPC Class Codes: G09G 2300/04 Structural and physical details of display devices
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

Claims

1. A semiconductor device comprising:

a pulse output circuit comprising a first transistor, a second transistor, and a third transistor,

wherein a gate of the first transistor, one of a source and a drain of the second transistor, and one of a source and a drain of the third transistor are directly connected to each other,

wherein one of a source and a drain of the first transistor is electrically connected to a signal line to which a clock signal is input, and

wherein the other of the source and the drain of the second transistor and the other of the source and the drain of the third transistor are arranged so that an output signal from a pulse output circuit in the preceding stage is input.

2. The semiconductor device according to claim 1, wherein each of the first transistor, the second transistor, and the third transistor includes a channel portion including an oxide semiconductor.

3. The semiconductor device according to claim 2, wherein the oxide semiconductor is InGaZnO.

4. The semiconductor device according to claim 1, wherein the other of the source and the drain of the third transistor is directly connected to the other of the source and the drain of the second transistor.

5. A semiconductor device comprising:

a first transistor, a second transistor, and a third transistor,

wherein a gate of the first transistor, one of a source and a drain of the second transistor, and one of a source and a drain of the third transistor are electrically connected to each other,

wherein the second transistor is a diode-connected transistor, and a gate of the second transistor is electrically connected to the other of the source and the drain of the second transistor, and

wherein the third transistor is a diode-connected transistor, and a gate of the third transistor is electrically connected to the one of the source and the drain of the third transistor.

6. The semiconductor device according to claim 5, wherein the gate of the first transistor, the one of the source and the drain of the second transistor, and the one of the source and the drain of the third transistor are directly connected to each other.

7. The semiconductor device according to claim 5, wherein each of the first transistor, the second transistor, and the third transistor includes a channel portion including an oxide semiconductor.

8. The semiconductor device according to claim 7, wherein the oxide semiconductor is InGaZnO.