Systems and methods for advanced ultra-high-performance InP solar cells

• US 10,026,856 B2
• Filed: 01/26/2017
• Issued: 07/17/2018
• Est. Priority Date: 03/27/2013
• Status: Active Grant

• Current Assignee: United States Department of Energy (Government of the United States of America)
• Original Assignee: Alliance For Sustainable Energy LLC
• Inventors: Wanlass, Mark
• Primary Examiner(s): Dinh, Bach T
• Application Number:
  US15/416,109
• Publication Number:
  US 20170133528A1
• Time in Patent Office: 537 Days
• Field of Search: 136243-265
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/0304 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 31/035272 characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/0693 the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
• CPC Class Codes: H01L 31/0735 comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
• CPC Class Codes: H01L 31/184 the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Systems and methods for advanced ultra-high-performance InP solar cells are provided. In one embodiment, an InP photovoltaic device comprises: a p-n junction absorber layer comprising at least one InP layer; a front surface confinement layer; and a back surface confinement layer; wherein either the front surface confinement layer or the back surface confinement layer forms part of a High-Low (HL) doping architecture; and wherein either the front surface confinement layer or the back surface confinement layer forms part of a heterointerface system architecture.

Claims

1. A photovoltaic device comprising:

a heterointerface system architecture comprising a front surface confinement layer and an emitter layer; and

a High-Low (HL) doping architecture comprising a back surface confinement layer and a base layer, wherein;

the emitter layer and the base layer form a p-n junction absorber layer,

at least one of the emitter layer or the base layer comprises InP, and

the back surface confinement layer comprises n-type InP and has a thickness of 7 nm or less.

2. The device of claim 1, wherein the p-n junction absorber layer includes a homojunction, and both the emitter layer and the base layer comprise InP.

3. The device of claim 1, wherein the p-n junction absorber layer includes a heterojunction.

4. The device of claim 1, wherein:

the base layer comprises n-type InP and is more lightly doped than the back surface confinement layer, and

a recombination rate is radiatively dominated in the base layer.

5. The device of claim 4, wherein the back surface confinement layer is doped degenerately.

6. The device of claim 1, wherein at least one of the front surface confinement layer or the emitter layer comprises p-type InP.

7. The device of claim 1, wherein the emitter layer comprises p-type InP, and the front surface confinement layer comprises one of:

GaAsSb, AlAsSb, AlGaAsSb, AlInAs, AlInAsSb, AlGaInAsSb, GaPSb, AlPSb, or AlGaPSb.

8. The device of claim 1, wherein the device has an ultra-thin cell structure.

9. The device of claim 1, further comprising a back surface reflector layer formed on the back surface confinement layer.

10. The device of claim 9, wherein the back surface reflector layer comprises one of:

a hybrid multi-layer-dielectric with a metal reflector;

an omnidirectional reflector (ODR) comprising a dielectric layer and a metal layer;

or

a broad-band high-low index distributed Bragg reflector (DBR) with high reflectance.

11. The device of claim 9, further comprising:

a contact layer electrically coupled to the back surface confinement layer; and

a metallization layer electrically coupled to the contact layer.

12. The device of claim 9, further comprising a metallization layer electrically coupled to the base layer.

13. The device of claim 1, wherein the at least one of the emitter layer or the base layer comprises a pseudo-binary alloy of InP containing up to 5% of at least one of Boron (B), Nitrogen (N), Aluminum (Al), Phosphorous (P), Gallium (Ga), Arsenic (As), Antimony (Sb), Indium (In), Thallium (Tl), or Bismuth (Bi).