Hierarchically elaborated phased-array antenna modules and method of operation

• US 10,027,028 B2
• Filed: 05/23/2016
• Issued: 07/17/2018
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Tubis Technology Inc
• Original Assignee: Tubis Technology Inc
• Inventors: Wang, James, Chie, Chak
• Primary Examiner(s): PHAN, DAO LINDA
• Application Number:
  US15/162,405
• Publication Number:
  US 20160268683A1
• Time in Patent Office: 785 Days
• Field of Search: 342 81, 342368, 342372, 342378, 342383, 375320, 375329
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 21/0025 Modular arrays
• CPC Class Codes: H01Q 21/061 Two dimensional planar arrays
• CPC Class Codes: H01Q 3/2605 Array of radiating elements provided with a feedback control over the element weights, e.g. adaptive arrays
• CPC Class Codes: H01Q 3/2629 Combination of a main antenna unit with an auxiliary antenna unit
• CPC Class Codes: H01Q 3/34 by electrical means active lenses or reflecting arrays H01Q3/46

Abstract

A method of operation for a hierarchically elaborated phased-array antenna. Within a plurality of front end modules a phased-array processing die individually transforms phase and gain according to a register array. The register array in each RFIC is grouped into a local register group and a global register group, the local registers physically placed close in proximity to RF chains which each correspond to an element of array antenna, whereby each set of local registers control an individual antenna element and a global register controlling overall RFIC function. The method efficiently elaborates phase shift weights into a submodule of a phase array antenna system. Within each subarray phase control submodule the method recursively elaborates weights to control phase shifters. The method receives and transforms pairs of major operators and minor operators. The method distributes to each submodule determining its own base phase shift weight per its unique configuration.

Claims

1. A method for operation of a phased-array antenna comprising at a submodule apparatus:

receiving a first major operand on a digital signal bus;

receiving a first and a second minor operand on the digital signal bus;

storing the first major operand as a base phase shift for the submodule into a register;

multiplying by a digital circuit the first minor operand with an index and

adding to the base phase shift to determine a first vector of phase shift weights for each of a plurality of shifters; and

multiplying by the digital circuit a second minor operand with an index and adding to each member of the first vector to determine phase shift weights for all the shifters wherein each antenna element comprises a phase shifter and gain equalizer coupled to a plurality of local registers which contain an antenna weight vector table.

2. The method of claim 1 further comprising:

receiving a second major operand on the digital signal bus;

multiplying by a digital circuit the first and second major operands with indexes to determine a base phase shift for each submodule according to its configuration; and

adding the phase shift error correction bias for each element of the antenna array into the antenna weight vector table.

3. The method of claim 1 for operation of a submodule apparatus further comprising:

receiving a first major operand on the digital signal bus;

receiving a first and a second minor operand on the digital signal bus;

storing the first major operand as a base phase shift for the submodule into a register;

recursively adding by a digital logic circuit a first minor operand to the base phase shift to determine a first vector of phase shift weights for each of a plurality of shifters; and

recursively adding a second minor operand to each member of the first vector in the antenna weight vector table to determine phase shift weights for all the shifters.

4. The method of claim 1 further comprising:

receiving a second major operand on the digital signal bus;

recursively adding the first and second major operands to determine and store into non-transitory computer readable media a base phase shift for each submodule according to its configuration; and

adding the phase shift error correction bias into the antenna weight vector table for each element of the antenna array.

5. The method of claim 4, the method further comprising:

determining a region that an antenna array of submodules will be pointing next R+1;

determining a condition that the region is adequately covered by one of a set of d phase weights previously associated with d directions for each element according to a content addressable memory store device wherein the phase weights are computed using an element index and a submodule index; and

when the condition is true, transmitting to each submodule an instruction to load a phase weight from the location d.

6. The method of claim 5 for controlling RFIC devices in an antenna array further comprising:

initializing common registers with calibrated gain values;

storing phase shifter values in local registers; and

determining antenna element phase and gain settings.

7. The method of claim 6 further comprising a lookup method for determining antenna element phase and gain settings, said lookup method comprising:

on the tabulation mode being set, accepting data transmitted on a data bus from the SPI master;

loading a binary representation of a phase vector table stored in non-transitory computer readable digital media into common local registers;

loading phase shifter values into appropriate local registers, and

looking up in non-transitory computer readable digital media gain settings and storing said gain settings for each associated phase shifter value into the local registers.

8. The method of claim 6 further comprising a method for determining antenna element phase and gain settings, said method comprising:

accepting data transmitted on a data bus from a SPI master; and

loading constants into Global and common local registers;

determining by digital multiplier and adder logic circuits phase shifter values per (Equation

     2) and loading the digital phase shifter values into appropriate local registers; and

,

looking up in non-transitory computer readable digital media gain settings and storing said gain settings for each associated phase shifter value into the local registers.