Switching controller circuit
First Claim
1. A switching controller circuit that is operable in at least one of first and second control modes, comprising:
- an analog control circuit that generates a pulse control signal in the first control mode, wherein the analog control circuit includes;
a peak-valley detector that receives an analog clock gate enable signal and generates the pulse control signal;
a comparator circuit that receives a reference signal, a load voltage signal, a clock signal, and the analog clock gate enable signal, and is connected to the peak-valley detector for receiving the pulse control signal, and that generates a comparator interrupt signal; and
a timer circuit that receives the analog clock gate enable signal, and is connected to the peak-valley detector for receiving the pulse control signal, and that generates a timer interrupt signal based on a predetermined count value;
a digital control circuit that generates a digital control signal in the second control mode, wherein the digital control circuit includes;
an analog-to-digital converter (ADC) circuit that receives the load voltage signal, the clock signal, and a digital clock gate enable signal and outputs a digitized load voltage signal; and
a processing circuit that receives a processing clock gate enable signal and the clock signal, and is connected to the ADC circuit for receiving the digitized load voltage signal, the timer circuit for receiving the timer interrupt signal, and the comparator circuit for receiving the comparator interrupt signal, wherein the processing circuit outputs control mode data and the digital control signal;
a clock enable circuit connected to the comparator circuit, the timer circuit, and the processing circuit for receiving the comparator interrupt signal, the timer interrupt signal, and the control mode data, respectively, wherein the clock enable circuit generates the analog clock gate enable signal, the digital clock gate enable signal, and the processing clock gate enable signal, wherein;
the switching controller circuit operates in the first control mode when the analog clock gate enable signal is active, and the digital clock gate enable signal and the processing clock gate enable signal are not active; and
the switching controller circuit operates in the second control mode when the analog clock gate enable signal is not active, and the digital clock gate enable signal and the processing clock gate enable signal are active; and
a digital pulse width modulation (PWM) circuit connected to the analog and digital control circuits, wherein the digital PWM circuit receives the pulse control signal from the analog control circuit when the clock enable circuit outputs the analog clock gate enable signal, the digital control signal from the digital control circuit when the clock enable circuit outputs the digital clock gate enable signal, and outputs a pulse wave signal corresponding to at least one of the pulse control signal and the digital control signal.
1 Assignment
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Accused Products
Abstract
A switching controller circuit for a power converter includes analog and digital control circuits, a clock enable circuit, and a digital pulse width modulation (PWM) circuit. When the power converter is in a standby mode, the switching controller circuit operates in an analog control mode by activating the analog control circuit. When the power converter is not in standby mode, the switching controller circuit activates the digital control circuit and operates in a digital control mode. The switching controller circuit uses inexpensive electronic components and consumes less power in the analog control mode, thereby reducing standby mode power consumption.
26 Citations
20 Claims
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1. A switching controller circuit that is operable in at least one of first and second control modes, comprising:
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an analog control circuit that generates a pulse control signal in the first control mode, wherein the analog control circuit includes; a peak-valley detector that receives an analog clock gate enable signal and generates the pulse control signal; a comparator circuit that receives a reference signal, a load voltage signal, a clock signal, and the analog clock gate enable signal, and is connected to the peak-valley detector for receiving the pulse control signal, and that generates a comparator interrupt signal; and a timer circuit that receives the analog clock gate enable signal, and is connected to the peak-valley detector for receiving the pulse control signal, and that generates a timer interrupt signal based on a predetermined count value; a digital control circuit that generates a digital control signal in the second control mode, wherein the digital control circuit includes; an analog-to-digital converter (ADC) circuit that receives the load voltage signal, the clock signal, and a digital clock gate enable signal and outputs a digitized load voltage signal; and a processing circuit that receives a processing clock gate enable signal and the clock signal, and is connected to the ADC circuit for receiving the digitized load voltage signal, the timer circuit for receiving the timer interrupt signal, and the comparator circuit for receiving the comparator interrupt signal, wherein the processing circuit outputs control mode data and the digital control signal; a clock enable circuit connected to the comparator circuit, the timer circuit, and the processing circuit for receiving the comparator interrupt signal, the timer interrupt signal, and the control mode data, respectively, wherein the clock enable circuit generates the analog clock gate enable signal, the digital clock gate enable signal, and the processing clock gate enable signal, wherein; the switching controller circuit operates in the first control mode when the analog clock gate enable signal is active, and the digital clock gate enable signal and the processing clock gate enable signal are not active; and the switching controller circuit operates in the second control mode when the analog clock gate enable signal is not active, and the digital clock gate enable signal and the processing clock gate enable signal are active; and a digital pulse width modulation (PWM) circuit connected to the analog and digital control circuits, wherein the digital PWM circuit receives the pulse control signal from the analog control circuit when the clock enable circuit outputs the analog clock gate enable signal, the digital control signal from the digital control circuit when the clock enable circuit outputs the digital clock gate enable signal, and outputs a pulse wave signal corresponding to at least one of the pulse control signal and the digital control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A switching controller circuit for a power converter that is operable in at least one of first and second control modes, the switching controller comprising:
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an analog control circuit that generates a pulse control signal in the first control mode, wherein the analog control circuit includes; a peak-valley detector that generates the pulse control signal based on an analog clock gate enable signal; a comparator circuit, connected to the peak-valley detector for receiving the pulse control signal, that generates a comparator interrupt signal based on the analog clock gate enable signal, wherein the comparator circuit includes; a comparator that receives a load voltage signal and a reference signal, and outputs a load output under-voltage signal; a window circuit, connected to the peak-valley detector and the comparator for receiving the pulse control signal and the load output under-voltage signal, respectively, that generates a windowed load output under-voltage signal; a filter circuit, connected to the window circuit for receiving the windowed load output under-voltage signal, that outputs a filtered load output under-voltage signal; and a multiplexer, connected to the window circuit and the filter circuit for receiving the windowed load output under-voltage signal and the filtered load output under-voltage signal, respectively, that outputs the comparator interrupt signal based on a filter enable signal; and a timer circuit, connected to the peak-valley detector for receiving the pulse control signal, that generates a timer interrupt signal based on the analog clock gate enable signal, wherein the timer circuit includes; a counter that generates a count signal based on a clock signal, the pulse control signal, and a reset signal; a capture circuit connected to the peak-valley detector for receiving the pulse control signal and generating the reset signal; and a compare circuit, connected to the counter that receives the count signal, that generates the timer interrupt signal based on a predetermined count value; a digital control circuit that generates a digital control signal in the second control mode, wherein the digital control circuit includes; an analog-to-digital converter (ADC) circuit that receives the load voltage signal and outputs a digitized load voltage signal based on a digital clock gate enable signal; and a processing circuit connected to the ADC circuit for receiving the digitized load voltage signal, the timer circuit for receiving the timer interrupt signal, and the comparator circuit for receiving the comparator interrupt signal, wherein the processing circuit generates control mode data and the digital control signal based on a processing clock gate enable signal; a clock enable circuit connected to the comparator circuit, the timer circuit, and the processing circuit for receiving the comparator interrupt signal, the timer interrupt signal, and the control mode data, respectively, wherein the clock enable circuit generates the analog clock gate enable signal, the digital clock gate enable signal, and the processing clock gate enable signal, wherein; the switching controller circuit operates in the first control mode when the analog clock gate enable signal is active, and the digital clock gate enable signal and the processing clock gate enable signal are not active, the switching controller circuit operates in the second control mode when the analog clock gate enable signal is not active, and the digital clock gate enable signal and the processing clock gate enable signal are active; and a digital pulse width modulation (PWM) circuit connected to the analog and digital control circuits, wherein the digital PWM circuit receives;
(i) the pulse control signal from the analog control circuit when the analog clock gate enable signal is active, (ii) the digital control signal from the digital control circuit when the digital clock gate enable signal is active, and (iii) outputs a pulse wave signal corresponding to one of the pulse control signal and the digital control signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification