Lockless multithreaded completion queue access
First Claim
1. A method, comprising:
- identifying a first number of processors in a computer;
identifying a second number of interrupt request (IRQ) lines on a hardware acceleration device in the computer and coupled to the processors, the second number greater than or equal to the first number;
associating, using a device driver by a first given one of the processors, each of the IRQ lines with one of the processors;
selecting, by the first given processor, a given IRQ line for an application thread;
identifying, by the first given processor, a second given one of the processors associated with the given IRQ line;
initiating, by the first given processor, execution of the application thread on the second given processor;
configuring through the device driver by the first given processor, using the given IRQ line, a completion queue for the application thread; and
prior to selecting the given IRQ line, identifying a plurality of event queues on the hardware acceleration device, and associating each of the IRQ lines with one of the event queues by the first given processor;
wherein a given one of the event queues is bound to the completion queue prior to the first given processor initiating execution of the application thread on the second given processor; and
wherein the second given processor is configured to lock the completion queue upon detecting that the given IRQ line is associated with a third given one of the processors by acquiring a spinlock for the completion queue, setting an processor owner flag to an invalid value, activating a read memory barrier, waiting for an in-use flag to clear, and releasing the spinlock.
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Accused Products
Abstract
Methods, computing systems and computer program products implement embodiments of the present invention that include identifying a first number of processors in a computer, and identifying a second number of interrupt request (IRQ) lines on a hardware acceleration device in the computer and coupled to the processors, the second number greater than or equal to the first number. Each of the IRQ lines is associated with one of the processors, and upon selecting a given IRQ line for an application thread, a given processor associated with the given IRQ line is identified. Execution of the application thread is initiated on the given processor, and using the given IRQ line, a completion queue is configured for the application thread. If the thread is executing on a different processor than the one managing the completion queue, then the management of the completion queue can be migrated to the processor executing the thread.
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Citations
17 Claims
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1. A method, comprising:
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identifying a first number of processors in a computer; identifying a second number of interrupt request (IRQ) lines on a hardware acceleration device in the computer and coupled to the processors, the second number greater than or equal to the first number; associating, using a device driver by a first given one of the processors, each of the IRQ lines with one of the processors; selecting, by the first given processor, a given IRQ line for an application thread; identifying, by the first given processor, a second given one of the processors associated with the given IRQ line; initiating, by the first given processor, execution of the application thread on the second given processor; configuring through the device driver by the first given processor, using the given IRQ line, a completion queue for the application thread; and prior to selecting the given IRQ line, identifying a plurality of event queues on the hardware acceleration device, and associating each of the IRQ lines with one of the event queues by the first given processor;
wherein a given one of the event queues is bound to the completion queue prior to the first given processor initiating execution of the application thread on the second given processor; and
wherein the second given processor is configured to lock the completion queue upon detecting that the given IRQ line is associated with a third given one of the processors by acquiring a spinlock for the completion queue, setting an processor owner flag to an invalid value, activating a read memory barrier, waiting for an in-use flag to clear, and releasing the spinlock. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An apparatus, comprising:
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a hardware acceleration device; a memory; and a first number of processors, wherein a first given one of the processors is configured; to identify a second number of interrupt request (IRQ) lines on the hardware acceleration device, the second number greater than or equal to the first number, to associate, using a device driver, each of the IRQ lines with one of the processors, to select a given IRQ line for an application thread, to identify a second given one of the processors associated with the given IRQ line, to initiate execution of the application thread on the second given processor, to configure through the device driver, in the memory and using the given IRQ line, a completion queue for the application thread, and prior to selecting the given IRQ line, to identify a plurality of event queues on the hardware acceleration device, and to associate each of the IRQ lines with one of the event queues by the first given processor;
wherein a given one of the event queues is bound to the completion queue prior to the first given processor initiating execution of the application thread on the second given processor; and
wherein the second given processor is configured to lock the completion queue upon detecting that the given IRQ line is associated with a third given one of the processors by acquiring a spinlock for the completion queue, setting an processor owner flag to an invalid value, activating a read memory barrier, waiting for an in-use flag to clear, and releasing the spinlock. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A computer program product, the computer program product comprising:
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a non-transitory computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising; computer readable program code configured to identify a first number of processors in a computer; computer readable program code configured to identify a second number of interrupt request (IRQ) lines on a hardware acceleration device in the computer and coupled to the processors, the second number greater than or equal to the first number; computer readable program code configured to associate, using a device driver by a first given one of the processors, each of the IRQ lines with one of the processors; computer readable program code configured to select, by the first given processor, a given IRQ line for an application thread; computer readable program code configured to identify, by the first given processor, a second given one of the processors associated with the given IRQ line; computer readable program code configured to initiate, by the first given processor, execution of the application thread on the second given processor; computer readable program code arranged to configure through the device driver by the first given processor, using the given IRQ line, a completion queue for the application thread; and computer readable program code configured, prior to selecting the given IRQ line, to identify a plurality of event queues on the hardware acceleration device, and to associate each of the IRQ lines with one of the event queues by the first given processor;
wherein a given one of the event queues is bound to the completion queue prior to the first given processor initiating execution of the application thread on the second given processor; and
wherein the second given processor is configured to lock the completion queue upon detecting that the given IRQ line is associated with a third given one of the processors by acquiring a spinlock for the completion queue, setting an processor owner flag to an invalid value, activating a read memory barrier, waiting for an in-use flag to clear, and releasing the spinlock. - View Dependent Claims (14, 15, 16, 17)
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Specification