Cache-based tracing for time travel debugging and analysis
First Claim
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1. A computer system, comprising:
- one or more processors, each including a corresponding processor data cache; and
one or more computer-readable media having stored thereon computer-executable instructions that are executable by the one or more processors to cause the computer system to record a replay-able trace of execution of an executable entity based on misses within a processor data cache, the computer-executable instructions including instructions that are executable to cause the computer system to perform at least the following;
execute one or more threads of the executable entity across one or more processing units of the one or more processors; and
during execution of the one or more threads, record a separate replay-able trace for each thread independently, including, for each thread;
recording initial processor register state for a particular processing unit, of the one or more processing units, that is executing the thread;
upon detecting a cache miss within the particular processing unit'"'"'s corresponding processor data cache based on execution of the thread, recording at least one line of cache data imported into the corresponding processor data cache in response to the processor data cache miss;
detecting an occurrence of a discontinuity in execution of the thread, wherein one or more entries are imported in the corresponding processor data cache during the discontinuity in execution of the thread; and
based at least on the occurrence of the discontinuity in execution of the thread, flushing the one or more imported entries in the corresponding processor data cache, wherein the flushed entries are not recorded in the separate replay-able trace.
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Abstract
Recording a replay-able trace of execution of an executable entity using cache data includes executing one or more threads of the executable entity concurrently across one or more processing units of the one or more processors. During execution of the one or more threads, a separate replay-able trace is recorded for each thread independently. Recording includes, for each thread, recording initial processor register state for the thread. Recording also includes, for each thread, and upon detecting a processor data cache miss, recording at least one line of cache data imported into the processor data cache.
97 Citations
26 Claims
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1. A computer system, comprising:
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one or more processors, each including a corresponding processor data cache; and one or more computer-readable media having stored thereon computer-executable instructions that are executable by the one or more processors to cause the computer system to record a replay-able trace of execution of an executable entity based on misses within a processor data cache, the computer-executable instructions including instructions that are executable to cause the computer system to perform at least the following; execute one or more threads of the executable entity across one or more processing units of the one or more processors; and during execution of the one or more threads, record a separate replay-able trace for each thread independently, including, for each thread; recording initial processor register state for a particular processing unit, of the one or more processing units, that is executing the thread; upon detecting a cache miss within the particular processing unit'"'"'s corresponding processor data cache based on execution of the thread, recording at least one line of cache data imported into the corresponding processor data cache in response to the processor data cache miss; detecting an occurrence of a discontinuity in execution of the thread, wherein one or more entries are imported in the corresponding processor data cache during the discontinuity in execution of the thread; and based at least on the occurrence of the discontinuity in execution of the thread, flushing the one or more imported entries in the corresponding processor data cache, wherein the flushed entries are not recorded in the separate replay-able trace. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method, implemented at a computer system that includes one or more processors, each including a corresponding processor data cache, for recording a replay-able trace of execution of an executable entity using cache data, the method comprising:
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executing one or more threads of the executable entity across one or more processing units of the one or more processors; and during execution of the one or more threads, recording a separate replay-able trace for each thread independently, including, for each thread; recording initial processor register state for a particular processing unit, of the one or more processors, that is executing for the thread; upon detecting a cache miss within the particular processing unit'"'"'s corresponding processor data cache based on execution of the thread, recording at least one line of cache data imported into the corresponding processor data cache in response to the processor data cache miss; detecting an occurrence of a discontinuity in execution of the thread, wherein one or more entries are imported in the corresponding processor data cache during the discontinuity in execution of the thread; and based at least on the occurrence of the discontinuity in execution of the thread, flushing the one or more imported entries in the corresponding processor data cache, wherein the flushed entries are not recorded in the separate replay-able trace. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
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25. A computer program product comprising one or more hardware storage devices having stored thereon computer-executable instructions that are executable by one or more processors to cause a computer system to record a replay-able trace of execution of an executable entity using cache data, the computer-executable instructions including instructions that are executable to cause the computer system to perform at least the following:
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execute one or more threads of the executable entity across one or more processing units of the one or more processors; and during execution of the one or more threads, record a separate replay-able trace for each thread independently, including, for each thread; recording initial processor register state for a particular processing unit, of the one or more processing units, that is executing the thread; upon detecting a cache miss within a processor data cache for the particular processing based on execution of the thread, recording at least one line of cache data imported into the processor data cache in response to the processor data cache miss; detecting an occurrence of a discontinuity in execution of the thread, wherein one or more entries are imported in the processor data cache during the discontinuity in execution of the thread; and based at least on the occurrence of the discontinuity in execution of the thread, flushing the one or more imported entries in the processor data cache, wherein the flushed entries are not recorded in the separate replay-able trace.
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26. A computer system, comprising:
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one or more processors that comprise a cache memory; and one or more computer-readable media having stored thereon computer-executable instructions that are executable by the one or more processors to cause the computer system to record a replay-able trace of execution of an executable entity using cache data in the cache memory, the computer-executable instructions including instructions that are executable to cause the computer system to perform at least the following; execute one or more threads of the executable entity across one or more processing units of the one or more processors; and during execution of the one or more threads, record a separate replay-able trace for each thread independently, including, for at least one thread; recording into the trace initial processor register state for the at least one thread; upon detecting a cache miss in the cache memory based on execution of the thread, recording into the trace a line of cache data imported into the cache memory in response to the cache miss; based on recording the at least one line of cache data into the trace, setting a bit for the line of cache data in the cache memory; after setting a bit for the line of cache data in the cache memory, detecting that another entity has subsequently written to the line of cache data in the cache memory; based at least on the other entity subsequently writing to the line of cache data in the cache memory, clearing the bit for the line of cache data; and based at least on clearing the bit for the line of cache data, flushing the line of cache data prior to further execution of the thread.
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Specification