Sensing amplifier to detect the memory cell current transition

• US 10,032,489 B1
• Filed: 03/15/2017
• Issued: 07/24/2018
• Est. Priority Date: 03/15/2017
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Chen, Yingchang, Wu, Xiaoxia
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US15/459,857
• Time in Patent Office: 496 Days
• Field of Search: None
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

This disclosure provides a method and apparatus for detecting a transition of a memory cell current from a first state to a second state. An example apparatus includes a memory cell, a supplemental current source, a comparator, a reference voltage and a reference current source in a configuration that allows for real time detection of the transition of a memory cell. Detection of a memory cell current transition is captured when the output of the comparator transitions from one state to a second state in response to a sensing voltage exceeding the reference voltage.

Claims

1. An apparatus comprising:

a memory cell;

a bit line connected to the memory cell;

a sensing voltage node connected to the bit line;

a comparator having a first input connected to the sensing voltage node and a second input connected to a reference voltage, the comparator circuit configured to;

compare a voltage at the sensing voltage node to the reference voltage; and

output a detection signal based on the comparison of the voltage at the sensing voltage node to the reference voltage;

a reference current source connected to the sensing voltage node and configured to provide a reference current to the sensing voltage node;

a supplemental current transistor connected to the sensing voltage node and configured to provide a supplemental current to the sensing voltage node in response to a current through the memory cell exceeding the reference current, the reference current source connected in parallel to the supplemental current transistor; and

a current limiter circuit connected to the reference current source and the supplemental current transistor, wherein the reference current source and the supplemental current transistor are connected in parallel between the current limiter circuit and the sensing voltage node.

2. The apparatus of claim 1, wherein the current limiter circuit comprises a limiting current source connected to a current mirror circuit, and wherein the current mirror circuit is further connected to both the reference current source and the supplemental current transistor.

3. The apparatus of claim 1, further comprising a pre-charge transistor connected to the sensing voltage node and configured to pre-charge the sensing voltage node prior to detection of a memory cell transition.

4. The apparatus of claim 3, wherein the pre-charge transistor is separate from the supplemental current transistor.

5. The apparatus of claim 1, wherein the comparator comprises an operational amplifier, and wherein the sensing voltage node is connected to a positive terminal of the operational amplifier and the reference voltage is connected to a negative terminal of the operational amplifier.

6. The apparatus of claim 1, further comprising a source-follower circuit connected to the bit line and the sensing voltage node, wherein the source follower circuit is configured to maintain a fixed voltage on the bit line.

7. The apparatus of claim 6, wherein the source-follower circuit comprises:

an operational amplifier having a positive input, a negative input, and an output; and

a first transistor having a gate connected to the output of the operational amplifier.

9. The apparatus of claim 7, wherein the source-follower circuit further comprises:

a second transistor having a gate connected to the output of the operational amplifier; and

a feedback path connected between a terminal of the operational amplifier and a source of the second transistor.

10. The apparatus of claim 1, wherein the supplemental current transistor comprises a drain connected to an output of the current limiter circuit and a source connected to the sensing voltage node.

8. An apparatus comprising:

a memory cell;

a bit line connected to the memory cell;

a sensing voltage node connected to the bit line;

a comparator having a first input connected to the sensing voltage node and a second input connected to a reference voltage, the comparator circuit configured to;

compare a voltage at the sensing voltage node to the reference voltage; and

output a detection signal based on the comparison of the voltage at the sensing voltage node to the reference voltage;

a reference current source connected to the sensing voltage node and configured to provide a reference current to the sensing voltage node;

a supplemental current transistor connected to the sensing voltage node and configured to provide a supplemental current to the sensing voltage node in response to a current through the memory cell exceeding the reference current, the reference current source connected in parallel to the supplemental current transistor; and

a source-follower circuit connected to the bit line and the sensing voltage node, wherein the source follower circuit is configured to maintain a fixed voltage on the bit line, and wherein the source-follower circuit comprises;

an operational amplifier having a positive input, a negative input, and an output; and

a first transistor having a gate connected to the output of the operational amplifier, wherein the first transistor further comprises a drain connected to the sensing voltage node and a source connected to the memory cell via the bit line.

11. A method comprising:

applying a reference current to a bit line associated with a memory cell;

during a first current state of the memory cell, activating a supplemental current transistor to provide supplemental current to the bit line associated with the memory cell;

detecting a transition of the memory cell from the first current state to a second current state in response to an amount of current on the bit line falling below a level of the reference current, wherein the amount of current on the bit line falling below the amount of the reference current causes the supplemental current transistor to deactivate and further causes a sensing voltage received at a comparator to exceed a reference voltage; and

limiting a maximum current on the bit line using a current limiter circuit, wherein the current limiter circuit comprises a limit current source and a current mirror connected to both the supplemental current transistor and a source of the reference current.

12. The method of claim 11, wherein the supplemental current is provided in response to a magnitude of a current in the memory cell during the first current state exceeding a magnitude of the reference current.

13. The method of claim 11, further comprising fixing a voltage on the bit line using a source-follower circuit.

14. The method of claim 11, wherein the reference current is supplied by a constant current source, and wherein the supplemental current transistor is connected in parallel to the constant current source.

15. The method of claim 11, wherein the comparator is an operational amplifier having the reference voltage connected to a first input of the operational amplifier, and wherein the sensing voltage is connected to a second input of the operational amplifier;

and

wherein the transition causes an output of the operational amplifier to transition from a first voltage to a second voltage higher than the first voltage.

16. An apparatus comprising:

means for applying a reference current to a bit line associated with a memory cell;

means for selectively providing supplemental current to the bit line associated with the memory cell, wherein the means for selectively providing supplemental current further comprises means for deactivating the supplemental current in response to an amount of current on the bit line exceeding an amount of the reference current;

means for detecting a transition of the memory cell from a first current state to a second current state in response to a sensing voltage exceeding a reference voltage, wherein the sensing voltage is dependent on the amount of current on the bit line; and

means for limiting a maximum current on the bit line, wherein the means for limiting comprises a limit current source and a current mirror connected to both the means for selectively providing supplemental current and the means for applying the reference current.

17. A method comprising:

programming a memory cell, wherein programming the memory cell comprises transitioning the memory cell from a first state to a second state;

performing an operation to determine whether the memory cell is in the first state or the second state, wherein performing the operation comprises comparing a sensing voltage at a sensing voltage node to a reference voltage, wherein the sensing voltage is based on a first current received at the sensing voltage node from a supplemental current transistor and a second current received at the sensing voltage node from a reference current source, and wherein a combination of the first current and the second current is limited by a current limiter circuit, wherein the current limiter circuit comprises a limit current source and a current mirror connected to both the supplemental current transistor and a source of the reference current.

18. The method of claim 17, wherein the operation further comprises verifying whether the memory cell has transitioned from the first state to the second state, wherein transition to the second state causes an amount of current on a bit line to fall below an amount of the second current from the reference current source, and wherein transition to the second state causes the supplemental current transistor to deactivate and further causes the sensing voltage to exceed the reference voltage.

19. The method of claim 18, further comprising producing an error if the memory cell is verified to not be in the second state after the programming the memory cell.