Semiconductor memory device including variable resistance element
First Claim
1. A semiconductor memory device comprising:
- a memory cell including a variable resistance element;
a first pulldown circuit including a first resistance element and a first transistor, one end of the first transistor being connected to one end of the first resistance element;
a first bit line connected to the memory cell and the first pulldown circuit;
a second transistor, one end of the second transistor being connected to the first bit line;
a sense circuit connected to the other end of the second transistor, the sense circuit including a first node; and
a sequencer configured to execute reading, the sequencer including a first NOR gate, a first input terminal of the first NOR gate being connected to the first node, a first signal being input into a second input terminal of the first NOR gate, and an output terminal of the first NOR gate being connected to a gate of the first transistor,wherein;
the sequencer sequentially executes a pulldown operation and a read operation in the reading,the first signal is set to a first logic level during the pulldown operation, and the first signal is set to a second logic level during the read operation, the first logic level being different from the second logic level, andduring the pulldown operation,a first voltage is applied to a gate of the second transistor, a voltage of the first bit line falls from a second voltage to a third voltage based on a signal at a third logic level output from the first NOR gate, anda voltage of the first node changes from a fourth voltage to a fifth voltage in response to a fall of the voltage of the first bit line from the second voltage to the third voltage, and the first NOR gate outputs a signal at a fourth logic level, the fourth logic level being different from the third logic level.
5 Assignments
0 Petitions
Accused Products
Abstract
According to one embodiment, a semiconductor memory device includes a memory cell including a variable resistance element, a first circuit including a first resistance element and a first transistor, a first bit line, a second transistor, and a sense circuit. The memory cell and the first circuit are connected to the first bit line. One end and the other end of the second transistor are connected to the first bit line and the sense circuit respectively. During a first operation before reading data of the memory cell a voltage of the first bit line falls to a first voltage and the first and second transistors are turned off in response to a fall of the voltage of the first bit line to the first voltage.
-
Citations
20 Claims
-
1. A semiconductor memory device comprising:
-
a memory cell including a variable resistance element; a first pulldown circuit including a first resistance element and a first transistor, one end of the first transistor being connected to one end of the first resistance element; a first bit line connected to the memory cell and the first pulldown circuit; a second transistor, one end of the second transistor being connected to the first bit line; a sense circuit connected to the other end of the second transistor, the sense circuit including a first node; and a sequencer configured to execute reading, the sequencer including a first NOR gate, a first input terminal of the first NOR gate being connected to the first node, a first signal being input into a second input terminal of the first NOR gate, and an output terminal of the first NOR gate being connected to a gate of the first transistor, wherein; the sequencer sequentially executes a pulldown operation and a read operation in the reading, the first signal is set to a first logic level during the pulldown operation, and the first signal is set to a second logic level during the read operation, the first logic level being different from the second logic level, and during the pulldown operation, a first voltage is applied to a gate of the second transistor, a voltage of the first bit line falls from a second voltage to a third voltage based on a signal at a third logic level output from the first NOR gate, and a voltage of the first node changes from a fourth voltage to a fifth voltage in response to a fall of the voltage of the first bit line from the second voltage to the third voltage, and the first NOR gate outputs a signal at a fourth logic level, the fourth logic level being different from the third logic level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A semiconductor memory device comprising:
-
a memory cell including a variable resistance element; a pulldown circuit including a first resistance element and a first transistor, one end of the first transistor being connected to one end of the first resistance element; a first bit line connected to the memory cell and the first pulldown circuit; a second transistor, one end of the second transistor being connected to the first bit line; a reference cell including a reference resistance element; a second pulldown circuit including a second resistance element and a third transistor, one end of the third transistor being connected to one end of the second resistance element; a second bit line connected to the reference cell and the second pulldown circuit; a fourth transistor, one end of the fourth transistor being connected to the second bit line; a sense circuit, the sense circuit including fifth to eighth transistors, a gate of the fifth transistor being connected to the other end of the second transistor, one end of the sixth transistor being connected to one end of the fifth transistor, a gate of the seventh transistor being connected to the other end of the fourth transistor, and one end of the seventh transistor being connected to one end of the eighth transistor and gates of the sixth and eighth transistors; and a sequencer including first and second NOR gates, a first input terminal of the first NOR gate being connected to the one end of the fifth transistor, a first signal being input into a second input terminal of the first NOR gate, an output terminal of the first NOR gate being connected to a gate of the first transistor, a first input terminal of the second NOR gate being connected to the one end of the seventh transistor, the first signal being input into a second input terminal of the second NOR gate, and an output terminal of the second NOR gate being connected to a gate of the third transistor. - View Dependent Claims (19, 20)
-
Specification