Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
First Claim
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1. A semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises;
a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell;
a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto;
a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and
wherein said buried layer region is commonly connected to at least two of said memory cells.
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Abstract
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
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Citations
20 Claims
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1. A semiconductor memory array comprising:
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a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises; a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell; a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto; a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and wherein said buried layer region is commonly connected to at least two of said memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor memory array comprising:
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a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises; a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell; a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto; a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and a buried layer terminal electrically connected to said buried layer region; wherein when a first memory cell of said plurality of semiconductor memory cells is in a first charge level and a second memory cell of said plurality of semiconductor memory cells is in a second charge level, upon said transfer of data, said first memory cell stores a first nonvolatile memory state and second memory cell stores a second nonvolatile memory state, said first and second nonvolatile memory states being non-algorithmically determined by said first and second charge levels of said first and second memory cells, respectively. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification