Memory device including extra capacity and stacked memory device including the same

• US 10,032,523 B2
• Filed: 03/06/2017
• Issued: 07/24/2018
• Est. Priority Date: 06/07/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Jongpil, Song, Hosung, Jung, Wonchang
• Primary Examiner(s): Huang, Min
• Application Number:
  US15/450,588
• Publication Number:
  US 20170352433A1
• Time in Patent Office: 505 Days
• Field of Search: 711114
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/787 using a fuse hierarchy
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices

Abstract

A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation, and when the first sub memory cell array is defective in a second mode of operation, the multiplexing circuit selects the second sub memory cell array and the third sub memory cell array. The control logic circuit selects the first mode of operation or the second mode of operation. The control logic circuit controls the multiplexing circuit so that the first, second and third sub memory cell arrays are connected to input or output pads.

Claims

1. A memory device, comprising:

a memory cell array including a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array;

a multiplexing circuit that selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation for data input/output (I/O) operations from/to an external device, and when the first sub memory cell array is defective in a second mode of operation, deselects the first sub memory cell array and selects the second sub memory cell array and the third sub memory cell array, wherein in the second mode of operation, the second sub memory cell array is used for repair of the first sub memory cell array; and

a control logic circuit that selects the first mode of operation or the second mode of operation, wherein the control logic circuit controls the multiplexing circuit so that the first and second sub memory cell arrays are connected to input or output pads, wherein the control logic circuit controls the third sub memory cell array so that the third sub memory cell array is connected to the input or output pads.

2. The memory device of claim 1, wherein the multiplexing circuit comprises:

a first read multiplexer array that selects the first sub memory cell array or the second sub memory cell array;

a second read multiplexer array that selects the second sub memory cell array or the third sub memory cell array;

a first write multiplexer array that selects the first sub memory cell array or the second sub memory cell array; and

a second write multiplexer array that selects the second sub memory cell array or the third sub memory cell array.

3. The memory device of claim 2, wherein in the first mode of operation, the second read multiplexer array selects the second sub memory cell array in a read operation, and

wherein in the first mode of operation, the second write multiplexer array selects the second sub memory cell array in a write operation.

4. The memory device of claim 2, wherein when the first memory cell array is defective in the second mode of operation,

the first read multiplexer array selects the second sub memory cell array in a read operation, and the first write multiplexer array selects the second sub memory cell array in a write operation.

5. The memory device of claim 2, wherein in the second mode of operation, when a defect does not exist in the first sub memory cell array and the second sub memory cell array, the second read multiplexer array selects the second sub memory cell array in a read operation, and when a defect exists in the first sub memory cell array or the second sub memory cell array, the second read multiplexer array selects the third sub memory cell array in the read operation, and

wherein in the second mode of operation, when a defect does not exist in the first sub memory cell array and the second sub memory cell array, the second write multiplexer array selects the second sub memory cell array in a write operation, and when a defect exists in the first sub memory cell array or the second sub memory cell array, the second write multiplexer array selects the third sub memory cell array in the write operation.

6. The memory device of claim 1, wherein the control logic circuit comprises:

a mode of operation set circuit that sets the first mode of operation or the second mode of operation; and

a multiplexer control circuit that controls the multiplexing circuit based on the set mode of operation.

7. The memory device of claim 6, wherein the control logic circuit further comprises a multiplexer that, in response to the set mode of operation, connects the third sub memory cell array to the input or output pads in the first mode of operation, or cuts the third sub memory cell array off from the input or output pads in the second mode of operation.

8. The memory device of claim 6, wherein the mode of operation set circuit comprises a fuse set for setting the first mode of operation or the second mode of operation.

9. The memory device of claim 6, wherein the multiplexer control circuit comprises a first fuse set corresponding to the first sub memory cell array, a second fuse set corresponding to the second sub memory cell array and a third fuse set corresponding to the third sub memory cell array.

10. A stacked memory device, comprising:

a plurality of memory dies; and

a buffer die that controls the plurality of memory dies,

wherein at least one of the memory dies comprises;

a first through silicon via (TSV) area including TSVs connected to the buffer die;

a memory cell array including a plurality of first sub memory cell arrays and a second sub memory cell array;

a multiplexing circuit that connects the plurality of first sub memory cell arrays and the second sub memory cell array to the first TSV area in a first mode for data input/output (I/O) operations from/to an external device, and in a second mode, the multiplexing circuit connects the plurality of first sub memory cell arrays and the second sub memory cell array, except for at least one failed cell array among the plurality of first sub memory cell arrays, to the first TSV area, wherein in the second mode the second sub memory cell array is used for repair of failed cells in the at least one failed cell array; and

a control logic circuit that selects the first mode or the second mode, controls the multiplexing circuit so that the plurality of first sub memory cell arrays is connected to first input or output pads, and controls the second sub memory cell array so that the second sub memory cell array is connected to the first input or output pads.

11. The stacked memory device of claim 10, wherein the buffer die comprises:

a second TSV area including TSVs connected to the plurality of memory dies; and

second input or output pads connected to the second TSV area.

12. The stacked memory device of claim 10, wherein the control logic circuit comprises:

a mode set circuit that sets the first mode or the second mode; and

a multiplexer control circuit that controls the multiplexing circuit based on the set mode.

13. The stacked memory device of claim 12, wherein the control logic circuit further comprises a multiplexer that, in response to the set mode, connects the second sub memory cell array to the first input or output pads in the first mode or cuts the second sub memory cell array off from the first input or output pads in the second mode.

14. The stacked memory device of claim 12, wherein the mode set circuit comprises a fuse set for setting the first mode or the second mode.

15. The stacked memory device of claim 12, wherein the multiplexer control circuit comprises a fuse set corresponding to each of the plurality of first sub memory cell arrays.

16. A memory device, comprising:

a memory cell array including a first sub memory cell array, a second sub memory cell array and a third sub memory cell array;

a multiplexing circuit that selects the first, second and third sub memory cell arrays in a first operating mode for data input/output operations from/to an external device, and when the second sub memory cell array is defective in a second operating mode, deselects the second sub memory cell array, and selects the first and the third sub memory cell arrays, wherein in the second mode operation, the third sub memory cell array is used for repair of the second sub memory cell array; and

a control logic circuit that selects the first operating mode or the second operating mode, wherein the control logic circuit controls the multiplexing circuit so that the first and the second sub memory cell arrays are connected to input or output pads, wherein the control logic circuit controls the third sub memory cell array so that the third sub memory cell array is connected to the input or output pads.

17. The memory device of claim 16, wherein the first and second sub memory cell arrays are disposed on a first memory die and the third sub memory cell array is disposed on a second memory die, the first and second memory dies being in a stacked configuration.

18. The memory device of claim 17, wherein in the second operating mode, when the first sub memory cell array is defective, data is written into the second or third sub memory cell arrays and a connection to the first sub memory cell array is physically cut.

19. The memory device of claim 17, wherein in the second operating mode, when the second sub memory cell array is defective, data is written into the first or third sub memory cell arrays and a connection to the second sub memory cell array is physically cut.

20. The memory device of claim 17, wherein the control logic circuit includes an operating mode set circuit for setting the first operating mode or the second operating mode by cutting fuses or in response to a mode register set (MRS) command.